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/Linux-v5.10/Documentation/devicetree/bindings/net/
Dsamsung-sxgbe.txt4 - compatible: Should be "samsung,sxgbe-v2.0a"
5 - reg: Address and length of the register set for the device
6 - interrupts: Should contain the SXGBE interrupts
7 These interrupts are ordered by fixed and follows variable
9 index 0 - this is fixed common interrupt of SXGBE and it is always
11 index 1 to 25 - 8 variable trasmit interrupts, variable 16 receive interrupts
13 - phy-mode: String, operation mode of the PHY interface.
15 - samsung,pbl: Integer, Programmable Burst Length.
17 - samsung,burst-map: Integer, Program the possible bursts supported by sxgbe
18 This is an integer and represents allowable DMA bursts when fixed burst.
[all …]
Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.50a
25 - snps,dwmac-3.610
26 - snps,dwmac-3.70a
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Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
[all …]
Dibm,emac.txt8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
[all …]
/Linux-v5.10/samples/pktgen/
Dpktgen_sample05_flow_per_thread.sh2 # SPDX-License-Identifier: GPL-2.0
4 # Script will generate one flow per thread (-t N)
5 # - Same destination IP
6 # - Fake source IPs for each flow (fixed based on thread number)
10 # separate-flow should not access shared variables/data. This script
20 [ -z "$DEST_IP" ] && DEST_IP="198.18.0.42"
21 [ -z "$DST_MAC" ] && DST_MAC="90:e2:ba:ff:ff:ff"
22 [ -z "$CLONE_SKB" ] && CLONE_SKB="0"
23 [ -z "$BURST" ] && BURST=32
24 [ -z "$COUNT" ] && COUNT="0" # Zero means indefinitely
[all …]
/Linux-v5.10/drivers/gpu/drm/nouveau/dispnv04/
Darb.c2 * Copyright 1993-2003 NVIDIA, Corporation
3 * Copyright 2007-2009 Stuart Bennett
38 int burst; member
63 pclk_freq = arb->pclk_khz; in nv04_calc_arb()
64 mclk_freq = arb->mclk_khz; in nv04_calc_arb()
65 nvclk_freq = arb->nvclk_khz; in nv04_calc_arb()
66 pagemiss = arb->mem_page_miss; in nv04_calc_arb()
67 cas = arb->mem_latency; in nv04_calc_arb()
68 bpp = arb->bpp; in nv04_calc_arb()
92 m1 = clwm + cbs - 512; in nv04_calc_arb()
[all …]
/Linux-v5.10/drivers/net/ethernet/stmicro/stmmac/
Ddwmac1000_dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
9 Copyright (C) 2007-2009 STMicroelectronics Ltd
24 pr_info("dwmac1000: Master AXI performs %s burst length\n", in dwmac1000_dma_axi()
25 !(value & DMA_AXI_UNDEF) ? "fixed" : "any"); in dwmac1000_dma_axi()
27 if (axi->axi_lpi_en) in dwmac1000_dma_axi()
29 if (axi->axi_xit_frm) in dwmac1000_dma_axi()
33 value |= (axi->axi_wr_osr_lmt & DMA_AXI_WR_OSR_LMT_MASK) << in dwmac1000_dma_axi()
37 value |= (axi->axi_rd_osr_lmt & DMA_AXI_RD_OSR_LMT_MASK) << in dwmac1000_dma_axi()
40 /* Depending on the UNDEF bit the Master AXI will perform any burst in dwmac1000_dma_axi()
[all …]
Ddwmac1000.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
108 #define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */
119 #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
177 #define GMAC_DEBUG_RXFSTS_MASK GENMASK(9, 8) /* MTL Rx FIFO Fill-level */
196 /*--- DMA BLOCK defines ---*/
201 /* Programmable burst length (passed thorugh platform)*/
202 #define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */
212 #define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */
[all …]
Ddwmac4_dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
22 pr_info("dwmac4: Master AXI performs %s burst length\n", in dwmac4_dma_axi()
23 (value & DMA_SYS_BUS_FB) ? "fixed" : "any"); in dwmac4_dma_axi()
25 if (axi->axi_lpi_en) in dwmac4_dma_axi()
27 if (axi->axi_xit_frm) in dwmac4_dma_axi()
31 value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) << in dwmac4_dma_axi()
35 value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) << in dwmac4_dma_axi()
38 /* Depending on the UNDEF bit the Master AXI will perform any burst in dwmac4_dma_axi()
43 switch (axi->axi_blen[i]) { in dwmac4_dma_axi()
[all …]
/Linux-v5.10/drivers/spi/
Dspi-meson-spicc.c7 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/clk-provider.h>
30 * - all transfers are cutted in 16 words burst because the FIFO hangs on
31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
33 * - CS management is dumb, and goes UP between every burst, so is really a
69 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
72 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
89 #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */
92 #define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */
104 #define SPICC_LBC_RO BIT(13) /* Loop Back Control Read-Only */
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/Linux-v5.10/arch/arm/boot/dts/
Domap3-n950-n9.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap3-n950-n9.dtsi - Device Tree file for Nokia N950 & N9 (common stuff)
13 cpu0-supply = <&vcc>;
23 compatible = "regulator-fixed";
24 regulator-name = "VEMMC";
25 regulator-min-microvolt = <2900000>;
26 regulator-max-microvolt = <2900000>;
28 startup-delay-us = <150>;
29 enable-active-high;
33 compatible = "regulator-fixed";
[all …]
Dimx7ulp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx7ulp-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx7ulp-pinfunc.h"
15 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <1>;
37 #address-cells = <1>;
[all …]
Domap-gpmc-smsc911x.dtsi1 // SPDX-License-Identifier: GPL-2.0
10 vddvario: regulator-vddvario {
11 compatible = "regulator-fixed";
12 regulator-name = "vddvario";
13 regulator-always-on;
16 vdd33a: regulator-vdd33a {
17 compatible = "regulator-fixed";
18 regulator-name = "vdd33a";
19 regulator-always-on;
26 bank-width = <2>;
[all …]
Domap-gpmc-smsc9221.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 vddvario: regulator-vddvario {
15 compatible = "regulator-fixed";
16 regulator-name = "vddvario";
17 regulator-always-on;
20 vdd33a: regulator-vdd33a {
21 compatible = "regulator-fixed";
22 regulator-name = "vdd33a";
23 regulator-always-on;
30 bank-width = <2>;
[all …]
Domap3-igep.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 /dts-v1/;
19 stdout-path = &uart3;
23 compatible = "ti,omap-twl4030";
28 vdd33: regulator-vdd33 {
29 compatible = "regulator-fixed";
30 regulator-name = "vdd33";
31 regulator-always-on;
38 pinctrl-single,pins = <
45 pinctrl-single,pins = <
[all …]
Dimx6sll.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright 2017-2018 NXP.
8 #include <dt-bindings/clock/imx6sll-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include "imx6sll-pinfunc.h"
14 #address-cells = <1>;
15 #size-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <0>;
[all …]
Dimx6sx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/clock/imx6sx-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6sx-pinfunc.h"
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
57 #address-cells = <1>;
[all …]
Dartpec6.dtsi2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
[all …]
Dimx6qdl.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 * pre-existing /chosen node to be available to insert the
54 compatible = "fsl,imx-ckil", "fixed-clock";
55 #clock-cells = <0>;
56 clock-frequency = <32768>;
[all …]
/Linux-v5.10/drivers/net/ethernet/toshiba/
Dspider_net.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Network device driver for Cell Processor-Based Blade and Celleb platform
188 * 0000000 fixed to 0
190 * 000000 fixed to 0
194 * 000000 fixed to 0
195 * 00 burst alignment: 128 bytes
196 * 11 burst alignment: 1024 bytes
198 * 00000 fixed to 0
/Linux-v5.10/Documentation/networking/device_drivers/ethernet/stmicro/
Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
[all …]
/Linux-v5.10/drivers/media/pci/cx18/
Dcx18-av-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Derived from cx25840-core.c
11 #include "cx18-driver.h"
12 #include "cx18-io.h"
13 #include "cx18-cards.h"
106 /* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz pre post-div*/ in cx18_av_init()
127 /* enable sleep mode - register appears to be read only... */ in cx18_av_initialize()
167 * Disable Video Auto-config of the Analog Front End and Video PLL. in cx18_av_initialize()
171 * 0x102 (CXADEC_CHIP_CTRL), 0x104-0x106 (CXADEC_AFE_CTRL), in cx18_av_initialize()
172 * 0x108-0x109 (CXADEC_PLL_CTRL1), and 0x10c-0x10f (CXADEC_VID_PLL_FRAC) in cx18_av_initialize()
[all …]
/Linux-v5.10/Documentation/networking/
Dpktgen.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Enable CONFIG_NET_PKTGEN to compile and build pktgen either in-kernel
31 overload type of benchmarking, as this could hurt the normal use-case.
35 # ethtool -G ethX tx 1024
44 ring-buffers for various performance reasons, and packets stalling
49 and the cleanup interval is affected by the ethtool --coalesce setting
50 of parameter "rx-usecs".
54 # ethtool -C ethX rx-usecs 30
72 * add_device DEVICE@NAME -- adds a single device
73 * rem_device_all -- remove all associated devices
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/dma/
Dste-dma40.txt4 - compatible: "stericsson,dma40"
5 - reg: Address range of the DMAC registers
6 - reg-names: Names of the above areas to use during resource look-up
7 - interrupt: Should contain the DMAC interrupt number
8 - #dma-cells: must be <3>
9 - memcpy-channels: Channels to be used for memcpy
12 - dma-channels: Number of channels supported by hardware - if not present
14 - disabled-channels: Channels which can not be used
18 dma: dma-controller@801c0000 {
19 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
[all …]
/Linux-v5.10/include/sound/
Dak4114.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
29 #define AK4114_REG_Pc0 0x12 /* burst preamble Pc byte 0 */
30 #define AK4114_REG_Pc1 0x13 /* burst preamble Pc byte 1 */
31 #define AK4114_REG_Pd0 0x14 /* burst preamble Pd byte 0 */
32 #define AK4114_REG_Pd1 0x15 /* burst preamble Pd byte 1 */
33 #define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */
34 #define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */
35 #define AK4114_REG_QSUB_INDEX 0x18 /* Q-subcode index */
36 #define AK4114_REG_QSUB_MINUTE 0x19 /* Q-subcode minute */
37 #define AK4114_REG_QSUB_SECOND 0x1a /* Q-subcode second */
[all …]

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