| /Linux-v6.6/drivers/usb/host/ |
| D | ehci-sh.c | 13 struct clk *iclk, *fclk; member
114 priv->fclk = devm_clk_get(&pdev->dev, "usb_fck"); in ehci_hcd_sh_probe()
115 if (IS_ERR(priv->fclk)) in ehci_hcd_sh_probe()
116 priv->fclk = NULL; in ehci_hcd_sh_probe()
122 clk_enable(priv->fclk); in ehci_hcd_sh_probe()
139 clk_disable(priv->fclk); in ehci_hcd_sh_probe()
157 clk_disable(priv->fclk); in ehci_hcd_sh_remove()
|
| D | ohci-at91.c | 54 struct clk *fclk; member
78 clk_set_rate(ohci_at91->fclk, 48000000); in at91_start_clock()
81 clk_prepare_enable(ohci_at91->fclk); in at91_start_clock()
90 clk_disable_unprepare(ohci_at91->fclk); in at91_stop_clock()
215 ohci_at91->fclk = devm_clk_get(dev, "uhpck"); in usb_hcd_at91_probe()
216 if (IS_ERR(ohci_at91->fclk)) { in usb_hcd_at91_probe()
218 retval = PTR_ERR(ohci_at91->fclk); in usb_hcd_at91_probe()
|
| /Linux-v6.6/Documentation/devicetree/bindings/display/ti/ |
| D | ti,omap4-dss.txt | 14 - clocks: handle to fclk
36 - clocks: handle to fclk
51 - clocks: handles to fclk and iclk
67 - clocks: handle to fclk
88 - clocks: handles to fclk and pll clock
111 - clocks: handles to fclk and pll clock
|
| D | ti,omap3-dss.txt | 14 - clocks: handle to fclk
37 - clocks: handle to fclk
52 - clocks: handles to fclk and iclk
64 - clocks: handle to fclk
82 - clocks: handles to fclk and pll clock
|
| D | ti,omap5-dss.txt | 14 - clocks: handle to fclk
36 - clocks: handle to fclk
51 - clocks: handles to fclk and iclk
69 - clocks: handles to fclk and pll clock
92 - clocks: handles to fclk and pll clock
|
| D | ti,dra7-dss.txt | 14 - clocks: handle to fclk
47 - clocks: handle to fclk
66 - clocks: handles to fclk and pll clock
|
| /Linux-v6.6/drivers/media/dvb-frontends/ |
| D | s5h1420.c | 39 u32 fclk; member
368 tmp = state->fclk / tmp; in s5h1420_read_status()
475 do_div(val, (state->fclk / 1000)); in s5h1420_setsymbolrate()
501 * divide fclk by 1000000 to get the correct value. */ in s5h1420_setfreqoffset()
502 val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000)); in s5h1420_setfreqoffset()
529 * divide fclk by 1000000 to get the correct value. */ in s5h1420_getfreqoffset()
530 val = (((-val) * (state->fclk/1000000)) / (1<<24)); in s5h1420_getfreqoffset()
666 /* set s5h1420 fclk PLL according to desired symbol rate */ in s5h1420_set_frontend()
668 state->fclk = 80000000; in s5h1420_set_frontend()
670 state->fclk = 59000000; in s5h1420_set_frontend()
[all …]
|
| D | cx24110.c | 50 {0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
231 u32 tmp, fclk, BDRI; in cx24110_set_symbolrate() local
245 and set the PLL accordingly (R07[1:0] Fclk, R06[7:4] PLLmult, in cx24110_set_symbolrate()
251 fclk=90999000UL/2; in cx24110_set_symbolrate()
255 fclk=60666000UL; in cx24110_set_symbolrate()
259 fclk=80888000UL; in cx24110_set_symbolrate()
263 fclk=90999000UL; in cx24110_set_symbolrate()
265 dprintk("cx24110 debug: fclk %d Hz\n",fclk); in cx24110_set_symbolrate()
275 BDRI=fclk>>2; in cx24110_set_symbolrate()
288 dprintk("fclk = %d\n", fclk); in cx24110_set_symbolrate()
|
| D | mb86a20s.h | 16 * @fclk: Clock frequency. If zero, assumes the default
22 u32 fclk; member
|
| /Linux-v6.6/drivers/clk/nuvoton/ |
| D | clk-ma35d1-pll.c | 146 unsigned long tmp, fout, fclk, diff; in ma35d1_pll_find_closest() local
153 fclk = div_u64(parent_rate * n, m); in ma35d1_pll_find_closest()
156 fclk = div_u64(fclk, 100); in ma35d1_pll_find_closest()
158 if (fclk < PLL_FCLK_MIN_FREQ || in ma35d1_pll_find_closest()
159 fclk > PLL_FCLK_MAX_FREQ) in ma35d1_pll_find_closest()
162 fout = div_u64(fclk, p); in ma35d1_pll_find_closest()
|
| /Linux-v6.6/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| D | smu_v13_0_1_ppsmc.h | 64 #define PPSMC_MSG_SetSoftMinFclk 0x14 ///< Set hard min for FCLK
68 #define PPSMC_MSG_GetFclkFrequency 0x18 ///< Get FCLK frequency
74 #define PPSMC_MSG_SetSoftMaxFclkByFreq 0x1E ///< Set soft max for FCLK
79 #define PPSMC_MSG_SetHardMinFclkByFreq 0x23 ///< Set hard min for FCLK
|
| D | smu_v13_0_4_ppsmc.h | 73 #define PPSMC_MSG_SetSoftMinFclk 0x14 ///< Set hard min for FCLK
79 #define PPSMC_MSG_GetFclkFrequency 0x18 ///< Get FCLK frequency
86 #define PPSMC_MSG_SetSoftMaxFclkByFreq 0x1E ///< Set soft max for FCLK
92 #define PPSMC_MSG_SetHardMinFclkByFreq 0x23 ///< Set hard min for FCLK
|
| /Linux-v6.6/drivers/iio/adc/ |
| D | ad7124.c | 262 unsigned int fclk, odr_sel_bits; in ad7124_set_channel_odr() local
264 fclk = clk_get_rate(st->mclk); in ad7124_set_channel_odr()
266 * FS[10:0] = fCLK / (fADC x 32) where: in ad7124_set_channel_odr()
268 * fCLK is the master clock frequency in ad7124_set_channel_odr()
272 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32); in ad7124_set_channel_odr()
281 /* fADC = fCLK / (FS[10:0] x 32) */ in ad7124_set_channel_odr()
282 st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32); in ad7124_set_channel_odr()
891 unsigned int fclk, power_mode; in ad7124_setup() local
894 fclk = clk_get_rate(st->mclk); in ad7124_setup()
895 if (!fclk) in ad7124_setup()
[all …]
|
| D | ad7192.c | 183 u32 fclk; member
540 fadc = DIV_ROUND_CLOSEST(st->fclk, in ad7192_get_available_filter_freq()
544 fadc = DIV_ROUND_CLOSEST(st->fclk, in ad7192_get_available_filter_freq()
548 fadc = DIV_ROUND_CLOSEST(st->fclk, AD7192_MODE_RATE(st->mode)); in ad7192_get_available_filter_freq()
668 fadc = DIV_ROUND_CLOSEST(st->fclk, in ad7192_get_3db_filter_freq()
716 *val = st->fclk / in ad7192_read_raw()
767 div = st->fclk / (val * st->f_order * 1024); in ad7192_write_raw()
1062 st->fclk = AD7192_INT_FREQ_MHZ; in ad7192_probe()
1072 st->fclk = clk_get_rate(st->mclk); in ad7192_probe()
1073 if (!ad7192_valid_external_frequency(st->fclk)) { in ad7192_probe()
|
| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| D | dcn314_clk_mgr.c | 452 /* We will not select WM based on fclk, so leave it as unconstrained */ in dcn314_build_watermark_ranges()
579 /* Find highest valid fclk pstate */ in dcn314_clk_mgr_helper_populate_bw_params()
581 if (is_valid_clock_value(clock_table->DfPstateTable[i].FClk) && in dcn314_clk_mgr_helper_populate_bw_params()
582 clock_table->DfPstateTable[i].FClk > max_fclk) { in dcn314_clk_mgr_helper_populate_bw_params()
583 max_fclk = clock_table->DfPstateTable[i].FClk; in dcn314_clk_mgr_helper_populate_bw_params()
588 /* We expect the table to contain at least one valid fclk entry. */ in dcn314_clk_mgr_helper_populate_bw_params()
603 uint32_t min_fclk = clock_table->DfPstateTable[0].FClk; in dcn314_clk_mgr_helper_populate_bw_params()
607 if (is_valid_clock_value(clock_table->DfPstateTable[j].FClk) && in dcn314_clk_mgr_helper_populate_bw_params()
608 clock_table->DfPstateTable[j].FClk < min_fclk && in dcn314_clk_mgr_helper_populate_bw_params()
610 min_fclk = clock_table->DfPstateTable[j].FClk; in dcn314_clk_mgr_helper_populate_bw_params()
[all …]
|
| /Linux-v6.6/arch/sh/drivers/pci/ |
| D | pcie-sh7786.c | 26 struct clk *fclk, phy_clk; member
224 port->fclk = clk_get(NULL, fclk_name); in pcie_clk_init()
225 if (IS_ERR(port->fclk)) { in pcie_clk_init()
226 ret = PTR_ERR(port->fclk); in pcie_clk_init()
230 clk_enable(port->fclk); in pcie_clk_init()
250 clk_disable(port->fclk); in pcie_clk_init()
251 clk_put(port->fclk); in pcie_clk_init()
|
| /Linux-v6.6/drivers/clocksource/ |
| D | timer-ti-dm.c | 122 struct clk *fclk; member
402 if (unlikely(!timer) || IS_ERR(timer->fclk)) in omap_dm_timer_set_source()
431 if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2) in omap_dm_timer_set_source()
441 ret = clk_set_parent(timer->fclk, parent); in omap_dm_timer_set_source()
713 if (timer && !IS_ERR(timer->fclk)) in omap_dm_timer_get_fclk()
714 return timer->fclk; in omap_dm_timer_get_fclk()
766 rate = clk_get_rate(timer->fclk); in omap_dm_timer_stop()
1124 timer->fclk = devm_clk_get(dev, "fck"); in omap_dm_timer_probe()
1125 if (IS_ERR(timer->fclk)) in omap_dm_timer_probe()
1126 return PTR_ERR(timer->fclk); in omap_dm_timer_probe()
[all …]
|
| /Linux-v6.6/Documentation/devicetree/bindings/mmc/ |
| D | ti-omap-hsmmc.txt | 92 swakeup | | fclk
98 In suspend the fclk is off and the module is dysfunctional. Even register reads
99 will fail. A small logic in the host will request fclk restore, when an
|
| /Linux-v6.6/drivers/pwm/ |
| D | pwm-omap-dmtimer.c | 159 struct clk *fclk; in pwm_omap_dmtimer_config() local
168 fclk = omap->pdata->get_fclk(omap->dm_timer); in pwm_omap_dmtimer_config()
169 if (!fclk) { in pwm_omap_dmtimer_config()
170 dev_err(chip->dev, "invalid pmtimer fclk\n"); in pwm_omap_dmtimer_config()
174 clk_rate = clk_get_rate(fclk); in pwm_omap_dmtimer_config()
176 dev_err(chip->dev, "invalid pmtimer fclk rate\n"); in pwm_omap_dmtimer_config()
|
| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| D | vg_clk_mgr.c | 399 /* We will not select WM based on fclk, so leave it as unconstrained */ in vg_build_watermark_ranges()
569 /* Find lowest DPM, FCLK is filled in reverse order*/ in vg_clk_mgr_helper_populate_bw_params()
572 if (clock_table->DfPstateTable[i].fclk != 0) { in vg_clk_mgr_helper_populate_bw_params()
587 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; in vg_clk_mgr_helper_populate_bw_params()
592 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; in vg_clk_mgr_helper_populate_bw_params()
629 { .fclk = 400, .memclk = 400, .voltage = 2800 },
630 { .fclk = 400, .memclk = 400, .voltage = 2800 },
631 { .fclk = 400, .memclk = 400, .voltage = 2800 },
632 { .fclk = 400, .memclk = 400, .voltage = 2800 }
|
| /Linux-v6.6/sound/soc/ti/ |
| D | omap-dmic.c | 36 struct clk *fclk; member
320 dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id); in omap_dmic_select_fclk()
330 mux = clk_get_parent(dmic->fclk); in omap_dmic_select_fclk()
476 dmic->fclk = devm_clk_get(dmic->dev, "fck"); in asoc_dmic_probe()
477 if (IS_ERR(dmic->fclk)) { in asoc_dmic_probe()
|
| /Linux-v6.6/drivers/clk/zynq/ |
| D | clkc.c | 102 static void __init zynq_clk_register_fclk(enum zynq_clk fclk, in zynq_clk_register_fclk() argument
146 clks[fclk] = clk_register_gate(NULL, clk_name, in zynq_clk_register_fclk()
151 if (clk_prepare_enable(clks[fclk])) in zynq_clk_register_fclk()
152 pr_warn("%s: FCLK%u enable failed\n", __func__, in zynq_clk_register_fclk()
153 fclk - fclk0); in zynq_clk_register_fclk()
170 clks[fclk] = ERR_PTR(-ENOMEM); in zynq_clk_register_fclk()
246 of_property_read_u32(np, "fclk-enable", &fclk_enable); in zynq_clk_setup()
|
| /Linux-v6.6/drivers/i2c/busses/ |
| D | i2c-omap.c | 297 * bus is busy. It will be changed to 1 on the next IP FCLK clock. in __omap_i2c_init()
355 struct clk *fclk; in omap_i2c_init() local
374 fclk = clk_get(omap->dev, "fck"); in omap_i2c_init()
375 if (IS_ERR(fclk)) { in omap_i2c_init()
376 error = PTR_ERR(fclk); in omap_i2c_init()
382 fclk_rate = clk_get_rate(fclk); in omap_i2c_init()
383 clk_put(fclk); in omap_i2c_init()
404 * The filter is iclk (fclk for HS) period. in omap_i2c_init()
413 fclk = clk_get(omap->dev, "fck"); in omap_i2c_init()
414 if (IS_ERR(fclk)) { in omap_i2c_init()
[all …]
|
| /Linux-v6.6/Documentation/devicetree/bindings/clock/ |
| D | zynq-7000.txt | 26 - fclk-enable : Bit mask to enable FCLKs statically at boot time.
28 FCLK will only be enabled if it is actually running at
|
| /Linux-v6.6/drivers/clk/imx/ |
| D | clk-imx1.c | 23 "prem", "fclk", };
51 clk[IMX1_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1); in mx1_clocks_init_dt()
|
