| /Linux-v6.1/drivers/cpufreq/ |
| D | s3c2412-cpufreq.c | 43 static struct clk *fclk; variable
52 unsigned long hclk, fclk, armclk, armdiv_clk; in s3c2412_cpufreq_calcdivs() local
55 fclk = cfg->freq.fclk; in s3c2412_cpufreq_calcdivs()
65 s3c_freq_dbg("%s: fclk=%lu, armclk=%lu, hclk_max=%lu\n", in s3c2412_cpufreq_calcdivs()
66 __func__, fclk, armclk, hclk_max); in s3c2412_cpufreq_calcdivs()
68 __func__, cfg->freq.fclk, cfg->freq.armclk, in s3c2412_cpufreq_calcdivs()
71 armdiv = fclk / armclk; in s3c2412_cpufreq_calcdivs()
79 armdiv_clk = fclk / armdiv; in s3c2412_cpufreq_calcdivs()
148 clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk); in s3c2412_cpufreq_setdivs()
157 .fclk = 200000000,
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| D | s3c2440-cpufreq.c | 46 static struct clk *fclk; variable
70 unsigned long hclk, fclk, armclk; in s3c2440_cpufreq_calcdivs() local
73 fclk = cfg->freq.fclk; in s3c2440_cpufreq_calcdivs()
77 s3c_freq_dbg("%s: fclk is %lu, armclk %lu, max hclk %lu\n", in s3c2440_cpufreq_calcdivs()
78 __func__, fclk, armclk, hclk_max); in s3c2440_cpufreq_calcdivs()
80 if (armclk > fclk) { in s3c2440_cpufreq_calcdivs()
81 pr_warn("%s: armclk > fclk\n", __func__); in s3c2440_cpufreq_calcdivs()
82 armclk = fclk; in s3c2440_cpufreq_calcdivs()
86 if (armclk < fclk && armclk < hclk_max) in s3c2440_cpufreq_calcdivs()
93 hclk = (fclk / hdiv); in s3c2440_cpufreq_calcdivs()
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| D | s3c2410-cpufreq.c | 45 unsigned long hclk, fclk, pclk; in s3c2410_cpufreq_calcdivs() local
49 fclk = cfg->freq.fclk; in s3c2410_cpufreq_calcdivs()
52 cfg->freq.armclk = fclk; in s3c2410_cpufreq_calcdivs()
54 s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n", in s3c2410_cpufreq_calcdivs()
55 __func__, fclk, hclk_max); in s3c2410_cpufreq_calcdivs()
57 hdiv = (fclk > cfg->max.hclk) ? 2 : 1; in s3c2410_cpufreq_calcdivs()
58 hclk = fclk / hdiv; in s3c2410_cpufreq_calcdivs()
84 .fclk = 200000000,
137 s3c2410_cpufreq_info.max.fclk = 266000000; in s3c2410a_cpufreq_add()
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| D | s3c24xx-cpufreq.c | 60 unsigned long fclk, pclk, hclk, armclk; in s3c_cpufreq_getcur() local
62 cfg->freq.fclk = fclk = clk_get_rate(clk_fclk); in s3c_cpufreq_getcur()
68 cfg->pll.frequency = fclk; in s3c_cpufreq_getcur()
72 cfg->divs.h_divisor = fclk / hclk; in s3c_cpufreq_getcur()
73 cfg->divs.p_divisor = fclk / pclk; in s3c_cpufreq_getcur()
80 cfg->freq.fclk = pll; in s3c_cpufreq_calc()
100 pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk, in s3c_cpufreq_show()
170 cpu_new.freq.fclk = cpu_new.pll.frequency; in s3c_cpufreq_settarget()
205 s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk); in s3c_cpufreq_settarget()
224 if (cpu_new.freq.fclk == cpu_cur.freq.fclk) { in s3c_cpufreq_settarget()
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| D | s3c24xx-cpufreq-debugfs.c | 33 f->fclk, f->hclk, f->pclk, f->armclk); in show_max()
75 seq_printf(seq, " FCLK %ld Hz\n", cfg->freq.fclk); in info_show()
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| /Linux-v6.1/drivers/usb/host/ |
| D | ehci-sh.c | 13 struct clk *iclk, *fclk; member
115 priv->fclk = devm_clk_get(&pdev->dev, "usb_fck"); in ehci_hcd_sh_probe()
116 if (IS_ERR(priv->fclk)) in ehci_hcd_sh_probe()
117 priv->fclk = NULL; in ehci_hcd_sh_probe()
123 clk_enable(priv->fclk); in ehci_hcd_sh_probe()
140 clk_disable(priv->fclk); in ehci_hcd_sh_probe()
158 clk_disable(priv->fclk); in ehci_hcd_sh_remove()
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| /Linux-v6.1/Documentation/devicetree/bindings/display/ti/ |
| D | ti,omap4-dss.txt | 14 - clocks: handle to fclk
36 - clocks: handle to fclk
51 - clocks: handles to fclk and iclk
67 - clocks: handle to fclk
88 - clocks: handles to fclk and pll clock
111 - clocks: handles to fclk and pll clock
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| D | ti,omap3-dss.txt | 14 - clocks: handle to fclk
37 - clocks: handle to fclk
52 - clocks: handles to fclk and iclk
64 - clocks: handle to fclk
82 - clocks: handles to fclk and pll clock
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| D | ti,omap5-dss.txt | 14 - clocks: handle to fclk
36 - clocks: handle to fclk
51 - clocks: handles to fclk and iclk
69 - clocks: handles to fclk and pll clock
92 - clocks: handles to fclk and pll clock
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| D | ti,dra7-dss.txt | 14 - clocks: handle to fclk
47 - clocks: handle to fclk
66 - clocks: handles to fclk and pll clock
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| /Linux-v6.1/include/linux/soc/samsung/ |
| D | s3c-cpu-freq.h | 20 * @fclk: The FCLK frequency in Hz.
34 unsigned long fclk; member
72 * @p_divisor: Divisor from FCLK to PCLK.
73 * @h_divisor: Divisor from FCLK to HCLK.
74 * @arm_divisor: Divisor from FCLK to ARMCLK (not all CPUs).
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| /Linux-v6.1/drivers/clk/samsung/ |
| D | clk-s3c2410.c | 57 MUX(FCLK, "fclk", fclk_p, CLKSLOW, 4, 1),
110 ALIAS(FCLK, NULL, "fclk"),
167 * armclk is directly supplied by the fclk, without
170 FFACTOR(ARMCLK, "armclk", "fclk", 1, 1, 0),
227 PNAME(hclk_p) = { "fclk", "div_hclk_2", "div_hclk_4", "div_hclk_3" };
228 PNAME(armclk_p) = { "fclk", "hclk" };
236 FFACTOR(0, "div_hclk_2", "fclk", 1, 2, 0),
254 DIV(0, "div_hclk", "fclk", CLKDIVN, 1, 1),
255 DIV_T(0, "div_hclk_4", "fclk", CAMDIVN, 9, 1, div_hclk_4_d),
256 DIV_T(0, "div_hclk_3", "fclk", CAMDIVN, 8, 1, div_hclk_3_d),
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| /Linux-v6.1/drivers/media/dvb-frontends/ |
| D | s5h1420.c | 39 u32 fclk; member
368 tmp = state->fclk / tmp; in s5h1420_read_status()
475 do_div(val, (state->fclk / 1000)); in s5h1420_setsymbolrate()
501 * divide fclk by 1000000 to get the correct value. */ in s5h1420_setfreqoffset()
502 val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000)); in s5h1420_setfreqoffset()
529 * divide fclk by 1000000 to get the correct value. */ in s5h1420_getfreqoffset()
530 val = (((-val) * (state->fclk/1000000)) / (1<<24)); in s5h1420_getfreqoffset()
666 /* set s5h1420 fclk PLL according to desired symbol rate */ in s5h1420_set_frontend()
668 state->fclk = 80000000; in s5h1420_set_frontend()
670 state->fclk = 59000000; in s5h1420_set_frontend()
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| D | cx24110.c | 50 {0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
231 u32 tmp, fclk, BDRI; in cx24110_set_symbolrate() local
245 and set the PLL accordingly (R07[1:0] Fclk, R06[7:4] PLLmult, in cx24110_set_symbolrate()
251 fclk=90999000UL/2; in cx24110_set_symbolrate()
255 fclk=60666000UL; in cx24110_set_symbolrate()
259 fclk=80888000UL; in cx24110_set_symbolrate()
263 fclk=90999000UL; in cx24110_set_symbolrate()
265 dprintk("cx24110 debug: fclk %d Hz\n",fclk); in cx24110_set_symbolrate()
275 BDRI=fclk>>2; in cx24110_set_symbolrate()
288 dprintk("fclk = %d\n", fclk); in cx24110_set_symbolrate()
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| D | mb86a20s.h | 16 * @fclk: Clock frequency. If zero, assumes the default
22 u32 fclk; member
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| /Linux-v6.1/arch/arm64/boot/dts/ti/ |
| D | k3-am62a-main.dtsi | 113 clock-names = "fclk";
123 clock-names = "fclk";
133 clock-names = "fclk";
143 clock-names = "fclk";
153 clock-names = "fclk";
163 clock-names = "fclk";
173 clock-names = "fclk";
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| /Linux-v6.1/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| D | smu_v13_0_1_ppsmc.h | 64 #define PPSMC_MSG_SetSoftMinFclk 0x14 ///< Set hard min for FCLK
68 #define PPSMC_MSG_GetFclkFrequency 0x18 ///< Get FCLK frequency
74 #define PPSMC_MSG_SetSoftMaxFclkByFreq 0x1E ///< Set soft max for FCLK
79 #define PPSMC_MSG_SetHardMinFclkByFreq 0x23 ///< Set hard min for FCLK
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| D | smu_v13_0_4_ppsmc.h | 73 #define PPSMC_MSG_SetSoftMinFclk 0x14 ///< Set hard min for FCLK
79 #define PPSMC_MSG_GetFclkFrequency 0x18 ///< Get FCLK frequency
86 #define PPSMC_MSG_SetSoftMaxFclkByFreq 0x1E ///< Set soft max for FCLK
92 #define PPSMC_MSG_SetHardMinFclkByFreq 0x23 ///< Set hard min for FCLK
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| /Linux-v6.1/drivers/iio/adc/ |
| D | ad7124.c | 262 unsigned int fclk, odr_sel_bits; in ad7124_set_channel_odr() local
264 fclk = clk_get_rate(st->mclk); in ad7124_set_channel_odr()
266 * FS[10:0] = fCLK / (fADC x 32) where: in ad7124_set_channel_odr()
268 * fCLK is the master clock frequency in ad7124_set_channel_odr()
272 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32); in ad7124_set_channel_odr()
281 /* fADC = fCLK / (FS[10:0] x 32) */ in ad7124_set_channel_odr()
282 st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32); in ad7124_set_channel_odr()
891 unsigned int fclk, power_mode; in ad7124_setup() local
894 fclk = clk_get_rate(st->mclk); in ad7124_setup()
895 if (!fclk) in ad7124_setup()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| D | dcn314_clk_mgr.c | 451 /* We will not select WM based on fclk, so leave it as unconstrained */ in dcn314_build_watermark_ranges()
578 /* Find highest valid fclk pstate */ in dcn314_clk_mgr_helper_populate_bw_params()
580 if (is_valid_clock_value(clock_table->DfPstateTable[i].FClk) && in dcn314_clk_mgr_helper_populate_bw_params()
581 clock_table->DfPstateTable[i].FClk > max_fclk) { in dcn314_clk_mgr_helper_populate_bw_params()
582 max_fclk = clock_table->DfPstateTable[i].FClk; in dcn314_clk_mgr_helper_populate_bw_params()
587 /* We expect the table to contain at least one valid fclk entry. */ in dcn314_clk_mgr_helper_populate_bw_params()
602 uint32_t min_fclk = clock_table->DfPstateTable[0].FClk; in dcn314_clk_mgr_helper_populate_bw_params()
606 if (is_valid_clock_value(clock_table->DfPstateTable[j].FClk) && in dcn314_clk_mgr_helper_populate_bw_params()
607 clock_table->DfPstateTable[j].FClk < min_fclk && in dcn314_clk_mgr_helper_populate_bw_params()
609 min_fclk = clock_table->DfPstateTable[j].FClk; in dcn314_clk_mgr_helper_populate_bw_params()
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| /Linux-v6.1/arch/sh/drivers/pci/ |
| D | pcie-sh7786.c | 26 struct clk *fclk, phy_clk; member
225 port->fclk = clk_get(NULL, fclk_name); in pcie_clk_init()
226 if (IS_ERR(port->fclk)) { in pcie_clk_init()
227 ret = PTR_ERR(port->fclk); in pcie_clk_init()
231 clk_enable(port->fclk); in pcie_clk_init()
251 clk_disable(port->fclk); in pcie_clk_init()
252 clk_put(port->fclk); in pcie_clk_init()
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| /Linux-v6.1/drivers/clocksource/ |
| D | timer-ti-dm.c | 123 struct clk *fclk; member
403 if (unlikely(!timer) || IS_ERR(timer->fclk)) in omap_dm_timer_set_source()
432 if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2) in omap_dm_timer_set_source()
442 ret = clk_set_parent(timer->fclk, parent); in omap_dm_timer_set_source()
701 if (timer && !IS_ERR(timer->fclk)) in omap_dm_timer_get_fclk()
702 return timer->fclk; in omap_dm_timer_get_fclk()
754 rate = clk_get_rate(timer->fclk); in omap_dm_timer_stop()
1112 timer->fclk = devm_clk_get(dev, "fck"); in omap_dm_timer_probe()
1113 if (IS_ERR(timer->fclk)) in omap_dm_timer_probe()
1114 return PTR_ERR(timer->fclk); in omap_dm_timer_probe()
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| /Linux-v6.1/Documentation/devicetree/bindings/mmc/ |
| D | ti-omap-hsmmc.txt | 92 swakeup | | fclk
98 In suspend the fclk is off and the module is disfunctional. Even register reads
99 will fail. A small logic in the host will request fclk restore, when an
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| /Linux-v6.1/drivers/pwm/ |
| D | pwm-omap-dmtimer.c | 159 struct clk *fclk; in pwm_omap_dmtimer_config() local
168 fclk = omap->pdata->get_fclk(omap->dm_timer); in pwm_omap_dmtimer_config()
169 if (!fclk) { in pwm_omap_dmtimer_config()
170 dev_err(chip->dev, "invalid pmtimer fclk\n"); in pwm_omap_dmtimer_config()
174 clk_rate = clk_get_rate(fclk); in pwm_omap_dmtimer_config()
176 dev_err(chip->dev, "invalid pmtimer fclk rate\n"); in pwm_omap_dmtimer_config()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| D | dcn315_clk_mgr.c | 376 /* We will not select WM based on fclk, so leave it as unconstrained */ in dcn315_build_watermark_ranges()
484 /* Find highest fclk pstate */ in dcn315_clk_mgr_helper_populate_bw_params()
486 if (clock_table->DfPstateTable[i].FClk > max_fclk) { in dcn315_clk_mgr_helper_populate_bw_params()
487 max_fclk = clock_table->DfPstateTable[i].FClk; in dcn315_clk_mgr_helper_populate_bw_params()
495 uint32_t min_fclk = clock_table->DfPstateTable[0].FClk; in dcn315_clk_mgr_helper_populate_bw_params()
499 && clock_table->DfPstateTable[j].FClk < min_fclk) { in dcn315_clk_mgr_helper_populate_bw_params()
500 min_fclk = clock_table->DfPstateTable[j].FClk; in dcn315_clk_mgr_helper_populate_bw_params()
715 DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n" in dcn315_clk_mgr_construct()
718 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk, in dcn315_clk_mgr_construct()
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