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Searched +full:exynos5433 +full:- +full:pcie (Results 1 – 12 of 12) sorted by relevance

/Linux-v6.1/Documentation/devicetree/bindings/pci/
Dsamsung,exynos-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC series PCIe Host Controller
10 - Marek Szyprowski <m.szyprowski@samsung.com>
11 - Jaehoon Chung <jh80.chung@samsung.com>
14 Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
15 PCIe IP and thus inherits all the common properties defined in
16 snps,dw-pcie.yaml.
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/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dsamsung,exynos-pcie-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,exynos-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC series PCIe PHY
10 - Marek Szyprowski <m.szyprowski@samsung.com>
11 - Jaehoon Chung <jh80.chung@samsung.com>
14 "#phy-cells":
18 const: samsung,exynos5433-pcie-phy
23 samsung,pmu-syscon:
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/Linux-v6.1/drivers/phy/samsung/
Dphy-exynos-pcie.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung Exynos SoC series PCIe PHY driver
5 * Phy provider for PCIe controller on Exynos SoC series
7 * Copyright (C) 2017-2020 Samsung Electronics Co., Ltd.
20 /* Sysreg FSYS register offsets and bits for Exynos5433 */
34 /* PMU PCIE PHY isolation control */
37 /* For Exynos pcie phy */
49 /* Exynos5433 specific functions */
54 regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET, in exynos5433_pcie_phy_init()
56 regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET, in exynos5433_pcie_phy_init()
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/Linux-v6.1/arch/arm64/boot/dts/exynos/
Dexynos5433.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC device tree source
7 * Samsung's Exynos5433 SoC device nodes are listed in this file.
8 * Exynos5433 based board files can include this file and provide
12 * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 compatible = "samsung,exynos5433";
21 #address-cells = <2>;
22 #size-cells = <2>;
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Dexynos5433-tm2-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5433 TM2 board device tree source
8 * which are based on Samsung Exynos5433 SoC.
11 /dts-v1/;
12 #include "exynos5433.dtsi"
13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/sound/samsung-i2s.h>
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Dexynos5433-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \
32 gpa0: gpa0-gpio-bank {
33 gpio-controller;
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/Linux-v6.1/drivers/usb/dwc3/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
74 Exynos5800, Exynos5433, Exynos7) ship with one DesignWare Core USB3
78 tristate "PCIe-based Platforms"
82 If you're using the DesignWare Core IP with a PCIe (but not HAPS
86 tristate "Synopsys PCIe-based HAPS Platforms"
90 If you're using the DesignWare Core IP with a Synopsys PCIe HAPS
/Linux-v6.1/Documentation/devicetree/bindings/mfd/
Dsyscon.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 represent as any specific type of device. The typical use-case is
13 for some other node's driver, or platform-specific code, to acquire
20 - Lee Jones <lee@kernel.org>
27 - syscon
30 - compatible
35 - items:
36 - enum:
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/Linux-v6.1/drivers/pci/controller/dwc/
Dpci-exynos.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Samsung Exynos SoCs
5 * Copyright (C) 2013-2020 Samsung Electronics Co., Ltd.
24 #include "pcie-designware.h"
26 #define to_exynos_pcie(x) dev_get_drvdata((x)->dev)
28 /* PCIe ELBI registers */
65 struct device *dev = ep->pci.dev; in exynos_pcie_init_clk_resources()
68 ret = clk_prepare_enable(ep->clk); in exynos_pcie_init_clk_resources()
70 dev_err(dev, "cannot enable pcie rc clock"); in exynos_pcie_init_clk_resources()
74 ret = clk_prepare_enable(ep->bus_clk); in exynos_pcie_init_clk_resources()
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/Linux-v6.1/drivers/clk/samsung/
Dclk-exynos5433.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Common Clock Framework support for Exynos5433 SoC.
10 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/exynos5433.h>
21 #include "clk-cpu.h"
22 #include "clk-pll.h"
769 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
771 PLL_36XX_RATE(24 * MHZ, 368639991U, 246, 4, 2, -15729),
772 PLL_36XX_RATE(24 * MHZ, 361507202U, 181, 3, 2, -16148),
773 PLL_36XX_RATE(24 * MHZ, 338687988U, 113, 2, 2, -6816),
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/Linux-v6.1/drivers/i2c/busses/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
16 for Cypress CCGx Type-C controller. Individual bus drivers
25 controller is part of the 7101 device, which is an ACPI-compliant
29 will be called i2c-ali1535.
37 controller is part of the 7101 device, which is an ACPI-compliant
41 will be called i2c-ali1563.
51 will be called i2c-ali15x3.
63 will be called i2c-amd756.
70 S4882 motherboard. On this 4-CPU board, the SMBus is multiplexed
76 will be called i2c-amd756-s4882.
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/Linux-v6.1/drivers/mfd/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
44 tristate "Active-semi ACT8945A"
49 Support for the ACT8945A PMIC from Active-semi. This device
50 features three step-down DC/DC converters and four low-dropout
66 sun4i-gpadc-iio and the hwmon driver iio_hwmon.
69 called sun4i-gpadc.
88 tablets etc. It has 4 DC/DC step-down regulators, 3 DC/DC step-down
119 over at91-usart-serial driver and usart-spi-driver. Only one function
135 tristate "Atmel HLCDC (High-end LCD Controller)"
172 tristate "X-Powers AC100"
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