Searched +full:external +full:- +full:control (Results 1 – 25 of 1049) sorted by relevance
12345678910>>...42
| /Linux-v6.1/Documentation/devicetree/bindings/clock/ |
| D | clk-palmas-clk32kg-clocks.txt | 5 This binding uses the common clock binding ./clock-bindings.txt.
8 - compatible : "ti,palmas-clk32kg" for clk32kg clock
9 "ti,palmas-clk32kgaudio" for clk32kgaudio clock
10 - #clock-cells : shall be set to 0.
13 - ti,external-sleep-control: The external enable input pins controlled the
14 enable/disable of clocks. The external enable input pins ENABLE1,
15 ENABLE2 and NSLEEP. The valid values for the external pins are:
20 via register access and these pins do not have any control.
21 The macros of external control pins for DTS is defined at
22 dt-bindings/mfd/palmas.h
[all …]
|
| D | pistachio-clock.txt | 5 general control, and top general control) which are instantiated individually
6 from the device-tree.
8 External clocks:
9 ----------------
11 There are three external inputs to the clock controllers which should be
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
18 ----------------------
[all …]
|
| D | baikal,bt1-ccu-div.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
16 connected with an external fixed rate oscillator, which signal is transformed
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
[all …]
|
| /Linux-v6.1/arch/m68k/include/asm/ |
| D | MC68328.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68328.h: '328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
26 * 0xFFFFF0xx -- System Control
31 * System Control Register (SCR)
36 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
39 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
42 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
52 * 0xFFFFF1xx -- Chip-Select logic
58 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
[all …]
|
| D | MC68EZ328.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
27 * 0xFFFFF0xx -- System Control
32 * System Control Register (SCR)
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
53 * 0xFFFFF1xx -- Chip-Select logic
84 #define CSA_EN 0x0001 /* Chip-Select Enable */
[all …]
|
| D | m5272sim.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5272sim.h -- ColdFire 5272 System Integration Module support.
67 #define MCFSIM_DCCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control */
70 #define MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */
75 #define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */
78 #define MCFSIM_PBCNT (MCF_MBAR + 0x88) /* Port B Control (r/w) */
83 #define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */
100 #define MCF_IRQ_EINT1 65 /* External Interrupt 1 */
101 #define MCF_IRQ_EINT2 66 /* External Interrupt 2 */
102 #define MCF_IRQ_EINT3 67 /* External Interrupt 3 */
[all …]
|
| D | MC68VZ328.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
5 * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
6 * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
9 * Based on include/asm-m68knommu/MC68332.h
29 * 0xFFFFF0xx -- System Control
34 * System Control Register (SCR)
39 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
[all …]
|
| /Linux-v6.1/drivers/pinctrl/samsung/ |
| D | pinctrl-samsung.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
65 * enum eint_type - possible external interrupt types.
66 * @EINT_TYPE_NONE: bank does not support external interrupts
67 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
68 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
69 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/regulator/ |
| D | lp872x.txt | 4 - compatible: "ti,lp8720" or "ti,lp8725"
5 - reg: I2C slave address. 0x7d = LP8720, 0x7a = LP8725
8 - ti,general-config: the value of LP872X_GENERAL_CFG register (u8)
10 bit[2]: BUCK output voltage control by external DVS pin or register
11 1 = external pin, 0 = bit7 of register 08h
12 bit[1]: sleep control by external DVS pin or register
13 1 = external pin, 0 = bit6 of register 08h
18 bit[4]: BUCK2 enable control. 1 = enable, 0 = disable
20 bit[2]: BUCK1 output voltage control by external DVS pin or register
22 bit[1]: LDO sleep control. 1 = sleep mode, 0 = normal
[all …]
|
| D | as3722-regulator.txt | 5 --------------------
7 regulator node. The AS3722 is having 7 DCDC step-down regulators as
8 sd[0-6], 10 LDOs as ldo[0-7], ldo[9-11]. The input supply of these
10 vsup-sd2-supply: Input supply for SD2.
11 vsup-sd3-supply: Input supply for SD3.
12 vsup-sd4-supply: Input supply for SD4.
13 vsup-sd5-supply: Input supply for SD5.
14 vin-ldo0-supply: Input supply for LDO0.
15 vin-ldo1-6-supply: Input supply for LDO1 and LDO6.
16 vin-ldo2-5-7-supply: Input supply for LDO2, LDO5 and LDO7.
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/mfd/ |
| D | as3722.txt | 4 -------------------
5 - compatible: Must be "ams,as3722".
6 - reg: I2C device address.
7 - interrupt-controller: AS3722 has internal interrupt controller which takes the
8 interrupt request from internal sub-blocks like RTC, regulators, GPIOs as well
9 as external input.
10 - #interrupt-cells: Should be set to 2 for IRQ number and flags.
12 of AS3722 are defined at dt-bindings/mfd/as3722.h
14 interrupts.txt, using dt-bindings/irq.
17 --------------------
[all …]
|
| D | stericsson,ab8500.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson Analog Baseband AB8500 and AB8505
10 - Linus Walleij <linus.walleij@linaro.org>
13 the AB8500 "Analog Baseband" is the mixed-signals integrated circuit
14 handling power management (regulators), analog-to-digital conversion
15 (ADC), battery charging, fuel gauging of the battery, battery-backed
16 RTC, PWM, USB PHY and some GPIO lines in the ST-Ericsson U8500 platforms
21 USB charging handling has changed, and it has an embedded USB-to-serial
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/phy/ |
| D | ti-phy.txt | 3 OMAP CONTROL PHY
6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
19 - reg : register ranges as listed in the reg-names property
20 - reg-names: "otghs_control" for control-phy-otghs
[all …]
|
| /Linux-v6.1/drivers/memory/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
34 bool "Atmel (Multi-port DDR-)SDRAM Controller"
39 This driver is for Atmel SDRAM Controller or Atmel Multi-port
40 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
42 LP-DDR memories.
53 Used to configure the EBI (external bus interface) when the device-
54 tree is used. This bus supports NANDs, external ethernet controller,
75 controller and specifically control the Self Refresh Power Down
79 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
83 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
[all …]
|
| /Linux-v6.1/arch/powerpc/include/asm/ |
| D | ipic.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * IPIC external definitions and structure.
36 #define IPIC_SICNR 0x28 /* System Internal Interrupt Control Register */
37 #define IPIC_SEPNR 0x2C /* System External Interrupt Pending Register */
40 #define IPIC_SEMSR 0x38 /* System External Interrupt Mask Register */
41 #define IPIC_SECNR 0x3C /* System External Interrupt Control Register */
44 #define IPIC_SERCR 0x48 /* System Error Control Register */
47 #define IPIC_SEFCR 0x58 /* System External Interrupt Force Register */
|
| /Linux-v6.1/Documentation/devicetree/bindings/usb/ |
| D | msm-hsusb.txt | 6 - compatible: Should contain "qcom,ehci-host"
7 - regs: offset and length of the register set in the memory map
8 - usb-phy: phandle for the PHY device
13 compatible = "qcom,ehci-host";
15 usb-phy = <&usb_otg>;
21 - compatible: Should contain:
22 "qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY
23 "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
25 - regs: Offset and length of the register set in the memory map
26 - interrupts: interrupt-specifier for the OTG interrupt.
[all …]
|
| D | ci-hdrc-usb2.txt | 4 - compatible: should be one of:
5 "fsl,imx23-usb"
6 "fsl,imx27-usb"
7 "fsl,imx28-usb"
8 "fsl,imx6q-usb"
9 "fsl,imx6sl-usb"
10 "fsl,imx6sx-usb"
11 "fsl,imx6ul-usb"
12 "fsl,imx7d-usb"
13 "fsl,imx7ulp-usb"
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
6 Some of these CSRs are used to control local interrupts connected to the core.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
11 attached to every HLIC: software interrupts, the timer interrupt, and external
13 timer interrupt comes from an architecturally mandated real-time timer that is
14 controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
16 via the platform-level interrupt controller (PLIC).
[all …]
|
| D | fsl,ls-extirq.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-extirq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Layerscape External Interrupt Controller
10 - Shawn Guo <shawnguo@kernel.org>
11 - Li Yang <leoyang.li@nxp.com>
15 LX216xA) support inverting the polarity of certain external interrupt
21 - enum:
22 - fsl,ls1021a-extirq
[all …]
|
| /Linux-v6.1/Documentation/networking/dsa/ |
| D | bcm_sf2.rst | 8 - xDSL gateways such as BCM63138
9 - streaming/multimedia Set Top Box such as BCM7445
10 - Cable Modem/residential gateways such as BCM7145/BCM3390
13 ports, offering a range of built-in and customizable interfaces:
15 - single integrated Gigabit PHY
16 - quad integrated Gigabit PHY
17 - quad external Gigabit PHY w/ MDIO multiplexer
18 - integrated MoCA PHY
19 - several external MII/RevMII/GMII/RGMII interfaces
21 The switch also supports specific congestion control features which allow MoCA
[all …]
|
| /Linux-v6.1/arch/mips/include/asm/sgi/ |
| D | hpc3.h | 40 u32 _unused0[0x1000/4 - 2]; /* padding */
41 volatile u32 pbdma_ctrl; /* pbus dma channel control register has
54 #define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */
58 u32 _unused1[0x1000/4 - 1]; /* padding */
61 /* The HPC3 SCSI registers, this does not include external ones. */
65 u32 _unused0[0x1000/4 - 2]; /* padding */
71 volatile u32 ctrl; /* control register */
78 #define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
89 #define HPC3_SDCFG_HW 0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
92 #define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */
[all …]
|
| /Linux-v6.1/drivers/usb/serial/ |
| D | keyspan_usa26msg.h | 1 /* SPDX-License-Identifier: BSD-3-Clause */
5 Copyright (C) 1998-2000 InnoSys Incorporated. All Rights Reserved
6 This file is available under a BSD-style copyright
19 Copyright (C) 1998-2000 InnoSys Incorporated. All Rights Reserved
21 This file is available under a BSD-style copyright
44 USB OUT (host -> USAxx, transmit) messages contain a
52 USB IN (USAxx -> host, receive) messages begin with a status
100 1999apr14 add resetDataToggle to control message
102 2000jun01 add extended BSD-style copyright text
120 there are three types of "commands" sent in the control message:
[all …]
|
| /Linux-v6.1/drivers/regulator/ |
| D | tps65910-regulator.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * tps65910.c -- TI tps65910
352 return -EINVAL; in tps65910_get_ctrl_register()
386 return -EINVAL; in tps65911_get_ctrl_register()
396 reg = pmic->get_ctrl_reg(id); in tps65910_set_mode()
412 return -EINVAL; in tps65910_set_mode()
421 reg = pmic->get_ctrl_reg(id); in tps65910_get_mode()
500 return srvsel - 3; in tps65910_get_voltage_dcdc_sel()
508 return opvsel - 3; in tps65910_get_voltage_dcdc_sel()
510 return -EINVAL; in tps65910_get_voltage_dcdc_sel()
[all …]
|
| /Linux-v6.1/Documentation/driver-api/usb/ |
| D | power-management.rst | 1 .. _usb-power-management:
7 :Date: Last-updated: February 2014
11 ---------
17 * Changing the default idle-delay time
25 * USB Port Power Control
26 * User Interface for Port Power Control
31 -------------------------
35 component is ``suspended`` it is in a nonfunctional low-power state; it
37 ``resumed`` (returned to a functional full-power state) when the kernel
67 ----------------------
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/powerpc/nintendo/ |
| D | wii.txt | 11 - model : Should be "nintendo,wii"
12 - compatible : Should be "nintendo,wii"
16 This node represents the multi-function "Hollywood" chip, which packages
21 - compatible : Should be "nintendo,hollywood"
25 Represents the interface between the graphics processor and a external
30 - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi"
31 - reg : should contain the VI registers location and length
32 - interrupts : should contain the VI interrupt
36 Represents the data and control interface between the main processor
41 - compatible : should be "nintendo,hollywood-pi","nintendo,flipper-pi"
[all …]
|
12345678910>>...42
