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/Linux-v5.10/arch/arm/mach-shmobile/
Dsetup-rcar-gen2.c27 { .compatible = "renesas,r8a7742-cpg-mssr", .data = "extal" },
28 { .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" },
29 { .compatible = "renesas,r8a7744-cpg-mssr", .data = "extal" },
30 { .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" },
31 { .compatible = "renesas,r8a7791-cpg-mssr", .data = "extal" },
32 { .compatible = "renesas,r8a7793-cpg-mssr", .data = "extal" },
39 struct device_node *cpg, *extal; in get_extal_freq() local
49 extal = of_parse_phandle(cpg, "clocks", idx); in get_extal_freq()
51 if (!extal) in get_extal_freq()
54 of_property_read_u32(extal, "clock-frequency", &freq); in get_extal_freq()
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/display/bridge/
Drenesas,lvds.yaml112 - description: EXTAL input clock
121 # The LVDS encoder can use the EXTAL or DU_DOTCLKINx clocks.
124 - extal
128 - extal
132 - extal
196 clock-names = "fck", "dclkin.0", "extal";
227 clock-names = "fck", "dclkin.0", "extal";
/Linux-v5.10/drivers/clk/renesas/
Drcar-usb2-clock-sel.c40 bool extal; member
50 priv->extal, priv->xtal, val); in usb2_clock_sel_enable_extal_only()
52 if (priv->extal && !priv->xtal && val != CLKSET0_EXTAL_ONLY) in usb2_clock_sel_enable_extal_only()
58 if (priv->extal && !priv->xtal) in usb2_clock_sel_disable_extal_only()
172 priv->extal = !!clk_get_rate(clk); in rcar_usb2_clock_sel_probe()
181 if (!priv->extal && !priv->xtal) { in rcar_usb2_clock_sel_probe()
Dr8a779a0-cpg-mssr.c37 CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */
89 DEF_INPUT("extal", CLK_EXTAL),
208 * Clock combining OSC EXTAL predivider and a fixed divider in rcar_r8a779a0_cpg_clk_register()
225 * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC
237 /* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */
Dr8a77470-cpg-mssr.c39 DEF_INPUT("extal", CLK_EXTAL),
173 * MD EXTAL PLL0 PLL1 PLL3
188 /* EXTAL div PLL1 mult x2 PLL3 mult */
Dr8a77980-cpg-mssr.c53 DEF_INPUT("extal", CLK_EXTAL),
192 * MD EXTAL PLL2 PLL1 PLL3 OSC
204 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
Dr8a77995-cpg-mssr.c54 DEF_INPUT("extal", CLK_EXTAL),
195 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
203 /* EXTAL div PLL1 mult/div PLL3 mult/div */
Dr8a7745-cpg-mssr.c39 DEF_INPUT("extal", CLK_EXTAL),
190 * MD EXTAL PLL0 PLL1 PLL3
205 /* EXTAL div PLL1 mult PLL3 mult PLL0 mult */
Dr8a77970-cpg-mssr.c66 DEF_INPUT("extal", CLK_EXTAL),
177 * MD EXTAL PLL0 PLL1 PLL3
194 /* EXTAL div PLL1 mult/div PLL3 mult/div */
Dr8a7742-cpg-mssr.c39 DEF_INPUT("extal", CLK_EXTAL),
212 * MD EXTAL PLL0 PLL1 PLL3
231 /* EXTAL div PLL1 mult PLL3 mult */
Dr8a7743-cpg-mssr.c40 DEF_INPUT("extal", CLK_EXTAL),
206 * MD EXTAL PLL0 PLL1 PLL3
225 /* EXTAL div PLL1 mult PLL3 mult */
Dr8a774c0-cpg-mssr.c56 DEF_INPUT("extal", CLK_EXTAL),
250 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
258 /* EXTAL div PLL1 mult/div PLL3 mult/div */
Dr8a77990-cpg-mssr.c56 DEF_INPUT("extal", CLK_EXTAL),
257 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
265 /* EXTAL div PLL1 mult/div PLL3 mult/div */
Dr7s9210-cpg-mssr.c59 DEF_INPUT("extal", CLK_EXTAL),
120 /* If EXTAL is above 12MHz, then we know it is Mode 1 */ in r7s9210_update_clk_table()
/Linux-v5.10/Documentation/devicetree/bindings/rtc/
Drenesas,sh-rtc.yaml44 enum: [ fck, rtc_x1, rtc_x3, extal ]
76 clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
/Linux-v5.10/Documentation/devicetree/bindings/sound/
Dfsl,esai.txt30 "extal" The esai baud clock for esai controller used to
62 clock-names = "core", "extal", "fsys";
/Linux-v5.10/Documentation/devicetree/bindings/clock/
Drenesas,cpg-mssr.yaml64 - extal # All
118 clock-names = "extal", "extalr";
/Linux-v5.10/arch/arm64/boot/dts/renesas/
Dr8a779a0.dtsi37 extal_clk: extal {
77 clock-names = "extal", "extalr";
/Linux-v5.10/drivers/gpu/drm/rcar-du/
Drcar_lvds.c72 struct clk *extal; /* External clock */ member
336 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.extal, freq, &pll, in __rcar_lvds_pll_setup_d3_e3()
861 lvds->clocks.extal = rcar_lvds_get_clock(lvds, "extal", true); in rcar_lvds_get_clocks()
862 if (IS_ERR(lvds->clocks.extal)) in rcar_lvds_get_clocks()
863 return PTR_ERR(lvds->clocks.extal); in rcar_lvds_get_clocks()
874 if (!lvds->clocks.extal && !lvds->clocks.dotclkin[0] && in rcar_lvds_get_clocks()
877 "no input clock (extal, dclkin.0 or dclkin.1)\n"); in rcar_lvds_get_clocks()
/Linux-v5.10/arch/sh/kernel/cpu/sh4a/
Dclock-sh7722.c42 /* The dll block multiplies the 32khz r_clk, may be used instead of extal */
172 CLKDEV_CON_ID("extal", &extal_clk),
224 /* autodetect extal or dll configuration */ in arch_clk_init()
Dclock-sh7343.c39 /* The dll block multiplies the 32khz r_clk, may be used instead of extal */
188 CLKDEV_CON_ID("extal", &extal_clk),
256 /* autodetect extal or dll configuration */ in arch_clk_init()
Dclock-sh7366.c39 /* The dll block multiplies the 32khz r_clk, may be used instead of extal */
186 CLKDEV_CON_ID("extal", &extal_clk),
249 /* autodetect extal or dll configuration */ in arch_clk_init()
Dclock-sh7723.c43 /* The dll multiplies the 32khz r_clk, may be used instead of extal */
197 CLKDEV_CON_ID("extal", &extal_clk),
272 /* autodetect extal or dll configuration */ in arch_clk_init()
/Linux-v5.10/arch/sh/boards/
Dboard-urquell.c184 * Only handle the EXTAL case, anyone interfacing a crystal in urquell_clk_init()
190 clk = clk_get(NULL, "extal"); in urquell_clk_init()
/Linux-v5.10/arch/sh/boards/mach-sdk7786/
Dsetup.c195 * Only handle the EXTAL case, anyone interfacing a crystal in sdk7786_clk_init()
201 clk = clk_get(NULL, "extal"); in sdk7786_clk_init()

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