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/Linux-v6.1/arch/arm64/boot/dts/microchip/
Dsparx5_pcb135_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
17 compatible = "gpio-leds";
21 default-state = "off";
26 default-state = "off";
31 default-state = "off";
36 default-state = "off";
41 default-state = "off";
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/net/
Dcortina,gemini-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/cortina,gemini-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cortina Systems Gemini Ethernet Controller
10 - Linus Walleij <linus.walleij@linaro.org>
13 This ethernet controller is found in the Gemini SoC family:
19 const: cortina,gemini-ethernet
23 description: must contain the global registers and the V-bit and A-bit
26 "#address-cells":
[all …]
Dmarvell-orion-net.txt1 Marvell Orion/Discovery ethernet controller
4 The Marvell Discovery ethernet controller can be found on Marvell Orion SoCs
8 The Discovery ethernet controller is described with two levels of nodes. The
9 first level describes the ethernet controller itself and the second level
10 describes up to 3 ethernet port nodes within that controller. The reason for
11 the multiple levels is that the port registers are interleaved within a single
12 set of controller registers. Each port node describes port-specific properties.
16 only one port associated. Multiple ports are implemented as multiple single-port
20 * Ethernet controller node
23 - #address-cells: shall be 1.
[all …]
Dhisilicon-hip04-net.txt1 Hisilicon hip04 Ethernet Controller
3 * Ethernet controller node
6 - compatible: should be "hisilicon,hip04-mac".
7 - reg: address and length of the register set for the device.
8 - interrupts: interrupt for the device.
9 - port-handle: <phandle port channel>
11 port, port number connected to the controller
13 group, field in the pkg desc, in general, it is the same as the port.
14 - phy-mode: see ethernet.txt [1].
17 - phy-handle: see ethernet.txt [1].
[all …]
Dcavium-pip.txt1 * PIP Ethernet nexus.
3 The PIP Ethernet nexus can control several data packet input/output
6 ports might be an individual Ethernet PHY.
10 - compatible: "cavium,octeon-3860-pip"
14 - reg: The base address of the PIP's register bank.
16 - #address-cells: Must be <1>.
18 - #size-cells: Must be <0>.
21 - compatible: "cavium,octeon-3860-pip-interface"
25 - reg: The interface number.
27 - #address-cells: Must be <1>.
[all …]
Dkeystone-netcp.txt5 Ethernet packets. NetCP has a gigabit Ethernet (GbE) subsystem with a ethernet
6 switch sub-module to send and receive packets. NetCP also includes a packet
12 Keystone II SoC's also have a 10 Gigabit Ethernet Subsystem (XGbE) which
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
14 per Ethernet port.
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
[all …]
Dfsl-enetc.txt1 * ENETC ethernet device tree bindings
3 Depending on board design and ENETC port type (internal or
9 - reg : Specifies PCIe Device Number and Function
12 - compatible : Should be "fsl,enetc".
14 1. The ENETC external port is connected to a MDIO configurable phy
16 1.1. Using the local ENETC Port MDIO interface
18 In this case, the ENETC node should include a "mdio" sub-node
19 that in turn should contain the "ethernet-phy" node describing the
21 already defined in Documentation/devicetree/bindings/net/ethernet.txt or
26 - phy-handle : Phandle to a PHY on the MDIO bus.
[all …]
Dmarvell-pp2.txt1 * Marvell Armada 375 Ethernet Controller (PPv2.1)
2 Marvell Armada 7K/8K Ethernet Controller (PPv2.2)
3 Marvell CN913X Ethernet Controller (PPv2.3)
7 - compatible: should be one of:
8 "marvell,armada-375-pp2"
9 "marvell,armada-7k-pp2"
10 - reg: addresses and length of the register sets for the device.
11 For "marvell,armada-375-pp2", must contain the following register
13 - common controller registers
14 - LMS registers
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/net/dsa/
Dmediatek,mt7530.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek MT7530 and MT7531 Ethernet Switches
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
16 There are two versions of MT7530, standalone and in a multi-chip module.
18 MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN,
[all …]
Dqca8k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
14 describing a port needs to have a valid phandle referencing the internal PHY
15 it is connected to. This is because there is no N:N mapping of port and PHY
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
17 the switch node and declare the phandle for the port, referencing the internal
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
[all …]
Dmicrochip,lan937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LAN937x Ethernet Switch Series Tree Bindings
10 - UNGLinuxDriver@microchip.com
13 - $ref: dsa.yaml#
18 - microchip,lan9370
19 - microchip,lan9371
20 - microchip,lan9372
21 - microchip,lan9373
[all …]
Dmscc,ocelot.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vladimir Oltean <vladimir.oltean@nxp.com>
11 - Claudiu Manoil <claudiu.manoil@nxp.com>
12 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - UNGLinuxDriver@microchip.com
16 There are multiple switches which are either part of the Ocelot-1 family, or
20 them performs packet I/O primarily through an Ethernet port of the switch
21 (which is attached to an Ethernet port of the host), rather than through
[all …]
Ddsa-port.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/dsa-port.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet Switch port Device Tree Bindings
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Vivien Didelot <vivien.didelot@gmail.com>
15 Ethernet switch port Description
18 - $ref: /schemas/net/ethernet-controller.yaml#
[all …]
Ddsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet Switch Device Tree Bindings
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Vivien Didelot <vivien.didelot@gmail.com>
15 This binding represents Ethernet Switches which have a dedicated CPU
16 port. That port is usually connected to an Ethernet Controller of the
23 pattern: "^(ethernet-)?switch(@.*)?$"
[all …]
Drealtek.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: dsa.yaml#
13 - Linus Walleij <linus.walleij@linaro.org>
20 The SMI "Simple Management Interface" is a two-wire protocol using
21 bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does
23 SMI-based Realtek devices. The realtek-smi driver is a platform driver
26 The MDIO-connected switches use MDIO protocol to access their registers.
27 The realtek-mdio driver is an MDIO driver and it must be inserted inside
[all …]
Dvitesse,vsc73xx.txt9 Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
10 Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
11 Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
12 Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
17 reside inside a SPI bus device tree node, see spi/spi-bus.txt
19 When the chip is connected to a parallel memory bus and work in memory-mapped
25 - compatible: must be exactly one of:
30 - gpio-controller: indicates that this switch is also a GPIO controller,
32 - #gpio-cells: this must be set to <2> and indicates that we are a twocell
37 - reset-gpios: a handle to a GPIO line that can issue reset of the chip.
[all …]
/Linux-v6.1/arch/mips/boot/dts/cavium-octeon/
Docteon_3xxx.dts1 // SPDX-License-Identifier: GPL-2.0
6 * use. Because of this, it contains a super-set of the available
15 phy0: ethernet-phy@0 {
17 marvell,reg-init =
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
22 /* irq, blink-activity, blink-link */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
27 phy1: ethernet-phy@1 {
29 marvell,reg-init =
33 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
[all …]
Docteon_68xx.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
7 * use. Because of this, it contains a super-set of the available
11 compatible = "cavium,octeon-6880";
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&ciu2>;
17 compatible = "simple-bus";
18 #address-cells = <2>;
19 #size-cells = <2>;
[all …]
/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dfsl-lx2160a-bluebox3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2020-2021 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dorion5x-netgear-wnr854t.dts1 // SPDX-License-Identifier: GPL-2.0-only
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include "orion5x-mv88f5181.dtsi"
11 model = "Netgear WNR854-t";
12 compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
24 stdout-path = "serial0:115200n8";
33 gpio-keys {
34 compatible = "gpio-keys";
[all …]
/Linux-v6.1/drivers/infiniband/ulp/opa_vnic/
Dopa_vnic_encap.h26 * - Redistributions of source code must retain the above copyright
28 * - Redistributions in binary form must reproduce the above copyright
32 * - Neither the name of Intel Corporation nor the names of its
52 * and decapsulation of Ethernet packets
63 * ETHERNET MANAGEMENT
84 #define OPA_VNIC_EMA_DATA (OPA_MGMT_MAD_SIZE - IB_MGMT_VENDOR_HDR)
102 /* VNIC Ethernet link status */
118 * struct opa_vesw_info - OPA vnic switch information
119 * @fabric_id: 10-bit fabric id
120 * @vesw_id: 12-bit virtual ethernet switch id
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/clock/
Darmada3700-periph-clock.txt14 -----------------------------------
35 -----------------------------------
36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
37 1 gbe-core parent clock for Gigabit Ethernet core
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
43 7 gbe1-core Gigabit Ethernet core port 1
[all …]
/Linux-v6.1/drivers/net/ethernet/ti/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 If you have a network (Ethernet) card belonging to this class, say Y.
27 This driver supports TI's DaVinci Ethernet .
60 This driver supports TI's CPSW Ethernet Switch.
77 This driver supports TI's CPSW Ethernet Switch.
89 the CPSW Ethernet Switch and Keystone 2 1g/10g Switch Subsystem.
94 tristate "TI K3 AM654x/J721E CPSW Ethernet driver"
102 This driver supports TI K3 AM654/J721E CPSW2G Ethernet SubSystem.
103 The two-port Gigabit Ethernet MAC (MCU_CPSW0) subsystem provides
104 Ethernet packet communication for the device: One Ethernet port
[all …]
/Linux-v6.1/drivers/staging/octeon/
Dethernet.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2003-2007 Cavium Networks
23 #include "octeon-ethernet.h"
24 #include "ethernet-defines.h"
25 #include "ethernet-mem.h"
26 #include "ethernet-rx.h"
27 #include "ethernet-tx.h"
28 #include "ethernet-mdio.h"
29 #include "ethernet-util.h"
42 "\tPOW group to receive packets from. All ethernet hardware\n"
[all …]
/Linux-v6.1/arch/m68k/
DKconfig.devices1 # SPDX-License-Identifier: GPL-2.0
15 Use the power-on LED on your machine as a load meter. The exact
16 behavior is platform-dependent, but normally the flash frequency is
17 a hyperbolic function of the 5-minute load average.
19 # We have a dedicated heartbeat LED. :-)
52 tristate "NatFeat Ethernet support"
53 depends on ETHERNET && NATFEAT
56 which will emulate a regular ethernet device while presenting an
60 bool "Atari EtherNAT Ethernet support"
64 CT/60 extension port.
[all …]

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