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/Linux-v5.10/sound/pci/
Des1968.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Rewritted from card-es1938.c source.
27 * encoding. The codecs are almost always AC-97 compliant codecs,
88 #include <linux/dma-mapping.h>
102 #include <media/drv-intf/tea575x.h>
119 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 1-MAX */
121 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ variable
122 static int total_bufsize[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1024 };
123 static int pcm_substreams_p[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4 };
124 static int pcm_substreams_c[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1 };
[all …]
/Linux-v5.10/drivers/dma/
Dmpc512x_dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 * written by Hongjun Chen <hong-jun.chen@freescale.com>.
22 * - chunked transfers (described by s/g lists with more than one item) are
24 * - transfers on MPC8308 always start from software as this SoC does not have
26 * - memory <-> I/O memory transfer chunks of sizes of 1, 2, 4, 16 (for
35 #include <linux/dma-mapping.h>
98 u32 dmaerqh; /* DMA enable request high(channels 63~32) */
99 u32 dmaerql; /* DMA enable request low(channels 31~0) */
100 u32 dmaeeih; /* DMA enable error interrupt high(ch63~32) */
101 u32 dmaeeil; /* DMA enable error interrupt low(ch31~0) */
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/Linux-v5.10/Documentation/devicetree/bindings/regulator/
Drichtek,rtmv20-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rtmv20-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
15 (Enable/Fail), Enable pin to turn chip on, and Fail pin as fault indication.
27 wakeup-source: true
32 enable-gpios:
33 description: A connection of the 'enable' gpio line.
36 richtek,ld-pulse-delay-us:
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/Linux-v5.10/drivers/staging/vc04_services/bcm2835-camera/
Dbcm2835-camera.c1 // SPDX-License-Identifier: GPL-2.0
18 #include <media/videobuf2-vmalloc.h>
19 #include <media/videobuf2-dma-contig.h>
20 #include <media/v4l2-device.h>
21 #include <media/v4l2-ioctl.h>
22 #include <media/v4l2-ctrls.h>
23 #include <media/v4l2-fh.h>
24 #include <media/v4l2-event.h>
25 #include <media/v4l2-common.h>
29 #include "mmal-common.h"
[all …]
/Linux-v5.10/drivers/clk/bcm/
Dclk-cygnus.c16 #include <linux/clk-provider.h>
23 #include <dt-bindings/clock/bcm-cygnus.h>
24 #include "clk-iproc.h"
33 #define ASIU_DIV_VAL(o, es, hs, hw, ls, lw) \ argument
34 { .offset = o, .en_shift = es, .high_shift = hs, \
46 #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \ argument
49 #define ASIU_GATE_VAL(o, es) { .offset = o, .en_shift = es } argument
55 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
75 .enable = ENABLE_VAL(0x4, 6, 0, 12),
81 .enable = ENABLE_VAL(0x4, 7, 1, 13),
[all …]
Dclk-nsp.c16 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/bcm-nsp.h>
22 #include "clk-iproc.h"
36 #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \ argument
43 CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init);
60 .enable = ENABLE_VAL(0x4, 12, 6, 18),
66 .enable = ENABLE_VAL(0x4, 13, 7, 19),
72 .enable = ENABLE_VAL(0x4, 14, 8, 20),
78 .enable = ENABLE_VAL(0x4, 15, 9, 21),
84 .enable = ENABLE_VAL(0x4, 16, 10, 22),
[all …]
Dclk-ns2.c16 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/bcm-ns2.h>
22 #include "clk-iproc.h"
38 #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \ argument
61 .enable = ENABLE_VAL(0x0, 18, 12, 0),
67 .enable = ENABLE_VAL(0x0, 19, 13, 0),
73 .enable = ENABLE_VAL(0x0, 20, 14, 0),
79 .enable = ENABLE_VAL(0x0, 21, 15, 0),
85 .enable = ENABLE_VAL(0x0, 22, 16, 0),
91 .enable = ENABLE_VAL(0x0, 23, 17, 0),
[all …]
/Linux-v5.10/drivers/parisc/
Deisa_enumerator.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * eisa_enumerator.c - provide support for EISA adapters in PA-RISC machines
36 * little-endian on the big-endian PAROSC */
92 res->name = name; in configure_memory()
93 res->start = mem_parent->start + get_24(buf+len+2); in configure_memory()
94 res->end = res->start + get_16(buf+len+5)*1024; in configure_memory()
95 res->flags = IORESOURCE_MEM; in configure_memory()
182 res->name = board; in configure_port()
183 res->start = get_16(buf+len+1); in configure_port()
184 res->end = get_16(buf+len+1)+(c&HPEE_PORT_SIZE_MASK)+1; in configure_port()
[all …]
/Linux-v5.10/arch/powerpc/platforms/85xx/
Dxes_mpc85xx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * X-ES board-specific functionality
9 * Author: Nate Case <ncase@xes-inc.com>
23 #include <asm/pci-bridge.h>
36 #define MPC85xx_L2CTL_L2E 0x80000000 /* L2 enable */
81 * Legacy xMon firmware on some X-ES boards does not enable L2 in xes_mpc85xx_fixups()
84 for_each_node_by_name(np, "l2-cache-controller") { in xes_mpc85xx_fixups()
90 "fsl,mpc8548-l2-cache-controller") && in xes_mpc85xx_fixups()
92 "fsl,mpc8540-l2-cache-controller") && in xes_mpc85xx_fixups()
94 "fsl,mpc8560-l2-cache-controller")) in xes_mpc85xx_fixups()
[all …]
/Linux-v5.10/arch/x86/realmode/rm/
Dtrampoline_64.S1 /* SPDX-License-Identifier: GPL-2.0 */
15 * with 16-bit addressing and 16-bit data. CS has some value
24 * --full-contents --reloc to make sure there are no relocation
33 #include <asm/processor-flags.h>
49 mov %ax, %es
72 # Enable protected mode
85 /* SEV-ES supports non-zero IP for entry points - no alignment needed */
93 mov %ax, %es
112 movl %edx, %es
132 * Memory encryption is enabled but the SME enable bit for this
[all …]
/Linux-v5.10/arch/x86/kernel/
Dhead_32.S1 /* SPDX-License-Identifier: GPL-2.0 */
19 #include <asm/asm-offsets.h>
21 #include <asm/processor-flags.h>
22 #include <asm/msr-index.h>
31 #define pa(X) ((X) - __PAGE_OFFSET)
50 * Worst-case size of the kernel mapping we need to make:
60 * 32-bit kernel entrypoint; only used by the boot CPU. On entry,
61 * %esi points to the real-mode code as a 32-bit pointer.
76 movl %eax,%es
80 leal -__PAGE_OFFSET(%ecx),%esp
[all …]
/Linux-v5.10/drivers/staging/vc04_services/vchiq-mmal/
Dmmal-msg.h1 /* SPDX-License-Identifier: GPL-2.0 */
37 #include "mmal-msg-common.h"
38 #include "mmal-msg-format.h"
39 #include "mmal-msg-port.h"
40 #include "mmal-vchiq.h"
75 MMAL_MSG_PORT_ACTION_TYPE_ENABLE, /* Enable a port */
112 u32 status; /* enum mmal_msg_status - how does this differ to
130 /* request and reply to VC to enable a component */
136 u32 status; /* The component enable status */
165 union mmal_es_specific_format es; /* es type specific data */ member
[all …]
Dmmal-vchiq.c1 // SPDX-License-Identifier: GPL-2.0
27 #include <media/videobuf2-vmalloc.h>
29 #include "mmal-common.h"
30 #include "mmal-vchiq.h"
31 #include "mmal-msg.h"
81 "ENABLE",
94 msg_type_names[(MSG)->h.type], \
95 (MSG)->h.type, (MSG_LEN)); \
102 (MSG_LEN) - sizeof(struct mmal_msg_header), 1); \
108 msg_type_names[(MSG)->h.type], \
[all …]
/Linux-v5.10/drivers/net/ethernet/intel/ice/
Dice_flex_pipe.c1 // SPDX-License-Identifier: GPL-2.0
85 * ice_sect_id - returns section ID
109 hdr = (struct ice_buf_hdr *)buf->buf; in ice_pkg_val_buf()
111 section_count = le16_to_cpu(hdr->section_count); in ice_pkg_val_buf()
115 data_end = le16_to_cpu(hdr->data_end); in ice_pkg_val_buf()
133 (ice_seg->device_table + in ice_find_buf_table()
134 le32_to_cpu(ice_seg->device_table_count)); in ice_find_buf_table()
137 (nvms->vers + le32_to_cpu(nvms->table_count)); in ice_find_buf_table()
146 * call is made with the ice_seg parameter non-NULL; on subsequent calls,
156 state->buf_table = ice_find_buf_table(ice_seg); in ice_pkg_enum_buf()
[all …]
/Linux-v5.10/fs/ext4/
Dsuper.c1 // SPDX-License-Identifier: GPL-2.0
7 * Laboratoire MASI - Institut Blaise Pascal
16 * Big-endian to little-endian byte-swapping/bitmaps by
28 #include <linux/backing-dev.h>
70 struct ext4_super_block *es);
72 struct ext4_super_block *es);
92 * Note the difference between i_mmap_sem (EXT4_I(inode)->i_mmap_sem) and
93 * i_mmap_rwsem (inode->i_mmap_rwsem)!
96 * mmap_lock -> sb_start_pagefault -> i_mmap_sem (r) -> transaction start ->
97 * page lock -> i_data_sem (rw)
[all …]
/Linux-v5.10/arch/arm/mach-omap1/
Dlcd_dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/lcd_dma.c
5 * Extracted from arch/arm/plat-omap/dma.c
6 * Copyright (C) 2003 - 2008 Nokia Corporation
11 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
13 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
16 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
26 #include <linux/omap-dma.h>
133 int es; in set_b1_regs() local
142 es = 1; in set_b1_regs()
[all …]
/Linux-v5.10/arch/x86/boot/compressed/
Defi_thunk_64.S1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Early support for invoking 32-bit EFI services from a 64-bit kernel.
8 * restore the firmware's 32-bit GDT before we make EFI serivce calls,
9 * since the firmware's 32-bit IDT is still currently installed and it
12 * On the plus side, we don't have to worry about mangling 64-bit
13 * addresses into 32-bits because we're executing with an identity
14 * mapped pagetable and haven't transitioned to 64-bit virtual addresses
21 #include <asm/processor-flags.h>
34 movl %es, %eax
40 * Convert x86-64 ABI params to i386 ABI
[all …]
/Linux-v5.10/drivers/regulator/
Drtmv20-regulator.c1 // SPDX-License-Identifier: GPL-2.0+
74 gpiod_set_value(priv->enable_gpio, 1); in rtmv20_lsw_enable()
79 /* HW re-enable, disable cache only and sync regcache here */ in rtmv20_lsw_enable()
80 regcache_cache_only(priv->regmap, false); in rtmv20_lsw_enable()
81 ret = regcache_sync(priv->regmap); in rtmv20_lsw_enable()
98 regcache_cache_only(priv->regmap, true); in rtmv20_lsw_disable()
99 regcache_mark_dirty(priv->regmap); in rtmv20_lsw_disable()
101 gpiod_set_value(priv->enable_gpio, 0); in rtmv20_lsw_disable()
109 .enable = rtmv20_lsw_enable,
133 ret = regmap_read(priv->regmap, RTMV20_REG_LDIRQ, &val); in rtmv20_irq_handler()
[all …]
/Linux-v5.10/arch/x86/platform/pvh/
Dhead.S1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define _pa(x) ((x) - __START_KERNEL_map)
17 #include <asm/processor-flags.h>
28 * - `ebx`: contains the physical memory address where the loader has placed
30 * - `cr0`: bit 0 (PE) must be set. All the other writeable bits are cleared.
31 * - `cr4`: all bits are cleared.
32 * - `cs `: must be a 32-bit read/execute code segment with a base of ‘0’
34 * - `ds`, `es`: must be a 32-bit read/write data segment with a base of
37 * - `tr`: must be a 32-bit TSS (active) with a base of '0' and a limit
39 * - `eflags`: bit 17 (VM) must be cleared. Bit 9 (IF) must be cleared.
[all …]
/Linux-v5.10/drivers/net/ethernet/marvell/
Dmvneta.c7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
151 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
153 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
264 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
333 #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD)
336 ((addr >= txq->tso_hdrs_phys) && \
337 (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
340 (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
440 struct mvneta_ethtool_stats es; member
449 /* Pointer to the CPU-local NAPI struct */
[all …]
/Linux-v5.10/tools/testing/selftests/kvm/include/x86_64/
Dprocessor.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <asm/msr-index.h>
41 /* General Registers in 64-Bit Mode */
77 return ((uint64_t)desc->base3 << 32) | in get_desc64_base()
78 (desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24)); in get_desc64_base()
135 uint16_t es; in get_es() local
137 __asm__ __volatile__("mov %%es, %[es]" in get_es()
138 : /* output */ [es]"=rm"(es)); in get_es()
139 return es; in get_es()
366 * set_cpuid() - overwrites a matching cpuid entry with the provided value.
[all …]
/Linux-v5.10/drivers/dma/ti/
Domap-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
15 #include <linux/omap-dma.h>
22 #include "../virt-dma.h"
101 uint32_t en; /* number of elements (24-bit) */
102 uint32_t fn; /* number of frames (16-bit) */
120 uint8_t es; /* CSDP_DATA_TYPE_xxx */ member
250 struct omap_desc *d = to_omap_dma_desc(&vd->tx); in omap_dma_desc_free()
252 if (d->using_ll) { in omap_dma_desc_free()
253 struct omap_dmadev *od = to_omap_dma_dev(vd->tx.chan->device); in omap_dma_desc_free()
[all …]
/Linux-v5.10/include/linux/
Dfsl_devices.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
17 PHY CLK to become stable - 10ms*/
30 * Each sub-arch has its own master list of unique devices and
31 * enumerates them by enum fsl_devices in a sub-arch specific header
40 * - platform data structures: <driver>_platform_data
41 * - platform data device flags: FSL_<driver>_DEV_<FLAG>
42 * - platform data board flags: FSL_<driver>_BRD_<FLAG>
47 FSL_USB_VER_NONE = -1,
86 unsigned power_budget; /* hcd->power_budget */
89 unsigned es:1; /* need USBMODE:ES */ member
[all …]
/Linux-v5.10/drivers/rtc/
Drtc-ds2404.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/platform_data/rtc-ds2404.h>
51 ds2404_gpio[DS2404_RST].gpio = pdata->gpio_rst; in ds2404_gpio_map()
52 ds2404_gpio[DS2404_CLK].gpio = pdata->gpio_clk; in ds2404_gpio_map()
53 ds2404_gpio[DS2404_DQ].gpio = pdata->gpio_dq; in ds2404_gpio_map()
58 dev_err(&pdev->dev, "error mapping gpio %s: %d\n", in ds2404_gpio_map()
66 chip->gpio = ds2404_gpio; in ds2404_gpio_map()
70 while (--i >= 0) in ds2404_gpio_map()
133 while (length--) in ds2404_read_memory()
141 u8 ta01, ta02, es; in ds2404_write_memory() local
[all …]
/Linux-v5.10/drivers/soc/tegra/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # 32-bit ARM SoCs
8 bool "Enable support for Tegra20 family"
25 bool "Enable support for Tegra30 family"
39 bool "Enable support for Tegra114 family"
51 bool "Enable support for Tegra124 family"
63 # 64-bit ARM SoCs
72 Enable support for NVIDIA Tegra132 SoC, based on the Denver
75 Tegra124's "4+1" Cortex-A15 CPU complex.
84 Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1,
[all …]

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