Searched +full:erratum +full:- +full:a008585 (Results 1 – 5 of 5) sorted by relevance
/Linux-v6.1/Documentation/devicetree/bindings/timer/ |
D | arm,arch_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Marc Zyngier <marc.zyngier@arm.com> 11 - Mark Rutland <mark.rutland@arm.com> 13 ARM cores may have a per-core architected timer, which provides per-cpu timers, 17 The per-core architected timer is attached to a GIC to deliver its 18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC 24 - items: 25 - const: arm,cortex-a15-timer [all …]
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/Linux-v6.1/drivers/clocksource/ |
D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 60 bool "OMAP dual-mode timer driver" if ARCH_K3 || COMPILE_TEST 64 Enables the support for the TI dual-mode timer driver. 180 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture, 203 32-bit free running decrementing counters. 238 bool "Integrator-AP timer driver" if COMPILE_TEST 241 Enables support for the Integrator-AP timer. 266 available on many OMAP-like platforms. 285 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST 289 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores [all …]
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D | arm_arch_timer.c | 1 // SPDX-License-Identifier: GPL-2.0-only 28 #include <linux/arm-smccc.h> 76 [ARCH_TIMER_PHYS_SECURE_PPI] = "sec-phys", 79 [ARCH_TIMER_HYP_PPI] = "hyp-phys", 80 [ARCH_TIMER_HYP_VIRT_PPI] = "hyp-virt", 108 * 2) a roll-over time of not less than 40 years 117 return clamp_val(ilog2(min_cycles - 1) + 1, 56, 64); in arch_counter_get_width() 132 writel_relaxed((u32)val, timer->base + CNTP_CTL); in arch_timer_reg_write() 139 writeq_relaxed(val, timer->base + CNTP_CVAL_LO); in arch_timer_reg_write() 148 writel_relaxed((u32)val, timer->base + CNTV_CTL); in arch_timer_reg_write() [all …]
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/Linux-v6.1/arch/arm64/boot/dts/freescale/ |
D | fsl-ls2080a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for Freescale Layerscape-2080A family SoC. 5 * Copyright 2014-2016 Freescale Semiconductor, Inc. 12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 13 #include "fsl-ls208xa.dtsi" 18 compatible = "arm,cortex-a57"; 21 cpu-idle-states = <&CPU_PW20>; 22 next-level-cache = <&cluster0_l2>; 23 #cooling-cells = <2>; 28 compatible = "arm,cortex-a57"; [all …]
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D | fsl-ls1043a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for NXP Layerscape-1043A family SoC. 5 * Copyright 2014-2015 Freescale Semiconductor, Inc. 11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 #include <dt-bindings/gpio/gpio.h> 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; [all …]
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