Searched +full:erratum +full:- +full:161010101 (Results 1 – 4 of 4) sorted by relevance
| /Linux-v5.10/Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
25 - enum:
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| /Linux-v5.10/drivers/clocksource/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
163 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
186 32-bit free running decrementing counters.
240 bool "Integrator-AP timer driver" if COMPILE_TEST
243 Enables support for the Integrator-AP timer.
276 available on many OMAP-like platforms.
285 It has a 64-bit counter with update rate up to 1000MHz.
286 This counter is accessed via couple of 32-bit memory-mapped registers.
305 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
309 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
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| D | arm_arch_timer.c | 1 // SPDX-License-Identifier: GPL-2.0-only
99 writel_relaxed(val, timer->base + CNTP_CTL); in arch_timer_reg_write()
102 writel_relaxed(val, timer->base + CNTP_TVAL); in arch_timer_reg_write()
109 writel_relaxed(val, timer->base + CNTV_CTL); in arch_timer_reg_write()
112 writel_relaxed(val, timer->base + CNTV_TVAL); in arch_timer_reg_write()
130 val = readl_relaxed(timer->base + CNTP_CTL); in arch_timer_reg_read()
133 val = readl_relaxed(timer->base + CNTP_TVAL); in arch_timer_reg_read()
140 val = readl_relaxed(timer->base + CNTV_CTL); in arch_timer_reg_read()
143 val = readl_relaxed(timer->base + CNTV_TVAL); in arch_timer_reg_read()
223 _retries--; \
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| /Linux-v5.10/Documentation/arm64/ |
| D | silicon-errata.rst | 10 so-called "errata", which can cause it to deviate from the architecture
30 a Category A erratum into a Category C erratum. These are collectively
32 cases (e.g. those cases that both require a non-secure workaround *and*
36 the erratum in question, a Kconfig entry is added under "Kernel
37 Features" -> "ARM errata workarounds via the alternatives framework".
39 CPU is detected. For less-intrusive workarounds, a Kconfig option is not
41 a way that the erratum will not be hit.
49 +----------------+-----------------+-----------------+-----------------------------+
50 | Implementor | Component | Erratum ID | Kconfig |
53 +----------------+-----------------+-----------------+-----------------------------+
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