Searched +full:enet +full:- +full:phy +full:- +full:lane +full:- +full:swap (Results 1 – 13 of 13) sorted by relevance
/Linux-v6.1/Documentation/devicetree/bindings/net/ |
D | ethernet-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Ethernet PHY Generic Binding 10 - Andrew Lunn <andrew@lunn.ch> 11 - Florian Fainelli <f.fainelli@gmail.com> 12 - Heiner Kallweit <hkallweit1@gmail.com> 14 # The dt-schema tools will generate a select statement first by using 21 pattern: "^ethernet-phy(@[a-f0-9]+)?$" [all …]
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/Linux-v6.1/arch/arm64/boot/dts/broadcom/stingray/ |
D | bcm958742t.dts | 33 /dts-v1/; 35 #include "bcm958742-base.dtsi" 43 enet-phy-lane-swap; 47 mmc-ddr-1_8v;
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D | bcm958742k.dts | 4 * Copyright(c) 2016-2017 Broadcom. All rights reserved. 33 /dts-v1/; 35 #include "bcm958742-base.dtsi" 43 enet-phy-lane-swap; 47 mmc-ddr-1_8v; 59 pinctrl-0 = <&spi0_pins>; 60 pinctrl-names = "default"; 61 cs-gpios = <&gpio_hsls 34 0>; 65 compatible = "jedec,spi-nor"; 67 spi-max-frequency = <20000000>; [all …]
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/Linux-v6.1/arch/arm64/boot/dts/broadcom/northstar2/ |
D | ns2-svk.dts | 33 /dts-v1/; 39 compatible = "brcm,ns2-svk", "brcm,ns2"; 49 stdout-path = "serial0:115200n8"; 59 &enet { 113 spi-max-frequency = <5000000>; 114 spi-cpha; 115 spi-cpol; 118 pl022,slave-tx-disable = <0>; 119 pl022,com-mode = <0>; 120 pl022,rx-level-trig = <1>; [all …]
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/Linux-v6.1/arch/arm64/boot/dts/freescale/ |
D | imx8mp-phyboard-pollux-rdk.dts | 1 // SPDX-License-Identifier: GPL-2.0 7 /dts-v1/; 9 #include <dt-bindings/leds/leds-pca9532.h> 10 #include <dt-bindings/pwm/pwm.h> 11 #include "imx8mp-phycore-som.dtsi" 14 model = "PHYTEC phyBOARD-Pollux i.MX8MP"; 15 compatible = "phytec,imx8mp-phyboard-pollux-rdk", 16 "phytec,imx8mp-phycore-som", "fsl,imx8mp"; 19 stdout-path = &uart1; 22 reg_usdhc2_vmmc: regulator-usdhc2 { [all …]
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D | imx8mp-phycore-som.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 7 #include <dt-bindings/net/ti-dp83867.h> 11 model = "PHYTEC phyCORE-i.MX8MP"; 12 compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp"; 26 cpu-supply = <&buck2>; 30 cpu-supply = <&buck2>; 34 cpu-supply = <&buck2>; 38 cpu-supply = <&buck2>; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_fec>; [all …]
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D | imx8mp-tqma8mpql-mba8mpxl.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 3 * Copyright 2021-2022 TQ-Systems GmbH 4 * Author: Alexander Stein <alexander.stein@tq-group.com> 7 /dts-v1/; 9 #include <dt-bindings/leds/common.h> 10 #include <dt-bindings/net/ti-dp83867.h> 11 #include <dt-bindings/pwm/pwm.h> 12 #include "imx8mp-tqma8mpql.dtsi" 15 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL"; 16 compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; [all …]
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D | mba8mx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 3 * Copyright 2020-2021 TQ-Systems GmbH 6 #include <dt-bindings/net/ti-dp83867.h> 8 /* TQ-Systems GmbH MBa8Mx baseboard */ 12 compatible = "pwm-beeper"; 14 beeper-hz = <4000>; 15 amp-supply = <®_vcc_3v3>; 19 stdout-path = &uart3; 22 gpio-keys { 23 compatible = "gpio-keys"; [all …]
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D | imx8mm-phycore-som.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <dt-bindings/net/ti-dp83867.h> 11 model = "PHYTEC phyCORE-i.MX8MM"; 12 compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm"; 24 reg_vdd_3v3_s: regulator-vdd-3v3-s { 25 compatible = "regulator-fixed"; 26 regulator-always-on; 27 regulator-boot-on; 28 regulator-max-microvolt = <3300000>; 29 regulator-min-microvolt = <3300000>; [all …]
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/Linux-v6.1/drivers/net/phy/ |
D | dp83867.c | 1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for the Texas Instruments DP83867 PHY 12 #include <linux/phy.h> 17 #include <linux/nvmem-consumer.h> 19 #include <dt-bindings/net/ti-dp83867.h> 99 /* PHY CTRL bits */ 124 /* PHY STS bits */ 185 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol() 192 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol() 197 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol() [all …]
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D | dp83869.c | 1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for the Texas Instruments DP83869 PHY 12 #include <linux/phy.h> 16 #include <dt-bindings/net/ti-dp83869.h> 70 /* This is the same bit mask as the BMCR so re-use the BMCR default */ 158 struct dp83869_private *dp83869 = phydev->priv; in dp83869_read_status() 165 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported)) { in dp83869_read_status() 166 if (phydev->link) { in dp83869_read_status() 167 if (dp83869->mode == DP83869_RGMII_100_BASE) in dp83869_read_status() 168 phydev->speed = SPEED_100; in dp83869_read_status() [all …]
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D | broadcom.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * drivers/net/phy/broadcom.c 13 #include "bcm-phy-lib.h" 16 #include <linux/phy.h> 21 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask) 24 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask)) 26 MODULE_DESCRIPTION("Broadcom PHY driver"); 39 /* handling PHY's internal RX clock delay */ in bcm54xx_config_clock_delay() 42 if (phydev->interface == PHY_INTERFACE_MODE_RGMII || in bcm54xx_config_clock_delay() 43 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { in bcm54xx_config_clock_delay() [all …]
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/Linux-v6.1/arch/arm/boot/dts/ |
D | rk3288-phycore-som.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device tree file for Phytec phyCORE-RK3288 SoM 8 #include <dt-bindings/net/ti-dp83867.h> 13 compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288"; 29 ext_gmac: external-gmac-clock { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <125000000>; 33 clock-output-names = "ext_gmac"; 36 leds: user-leds { [all …]
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