Home
last modified time | relevance | path

Searched +full:emem +full:- +full:configuration (Results 1 – 16 of 16) sorted by relevance

/Linux-v6.1/arch/arm/boot/dts/
Dtegra30-asus-tf300t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
12 tf300t-init-hog {
13 gpio-hog;
15 output-low;
27 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
43 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
[all …]
Dtegra30-asus-tf300tg.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
12 tf300tg-init-hog {
13 gpio-hog;
28 output-low;
39 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
47 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
55 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
[all …]
Dtegra30-asus-tf201.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
19 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
27 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
43 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
51 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
57 /* Azurewave AW-NH615 BCM4329B1 */
[all …]
Dtegra30-asus-tf700t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
20 remote-endpoint = <&bridge_input>;
21 bus-width = <24>;
36 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
44 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
52 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
60 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
68 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
[all …]
Dtegra124-nyan-blaze-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 emc-timings-1 {
5 nvidia,ram-code = <1>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
14 timing-20400000 {
15 clock-frequency = <20400000>;
16 nvidia,parent-clock-frequency = <408000000>;
[all …]
Dtegra124-apalis-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
9 emc-timings-1 {
10 nvidia,ram-code = <1>;
12 timing-12750000 {
13 clock-frequency = <12750000>;
14 nvidia,parent-clock-frequency = <408000000>;
16 clock-names = "emc-parent";
19 timing-20400000 {
20 clock-frequency = <20400000>;
[all …]
Dtegra124-jetson-tk1-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 emc-timings-3 {
5 nvidia,ram-code = <3>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
14 timing-20400000 {
15 clock-frequency = <20400000>;
16 nvidia,parent-clock-frequency = <408000000>;
[all …]
Dtegra30-pegatron-chagall.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-opp.dtsi"
10 #include "tegra30-cpu-opp-microvolt.dtsi"
11 #include "tegra30-asus-lvds-display.dtsi"
16 chassis-type = "tablet";
35 * pre-existing /chosen node to be available to insert the
[all …]
Dtegra30-asus-nexus7-grouper-memory-timings.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 memory-controller@7000f000 {
5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
8 timing-25500000 {
9 clock-frequency = <25500000>;
11 nvidia,emem-configuration = <
33 timing-51000000 {
34 clock-frequency = <51000000>;
36 nvidia,emem-configuration = <
[all …]
Dtegra124-nyan-big-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 nvidia,long-ram-code;
8 emc-timings-1 {
9 nvidia,ram-code = <1>;
11 timing-12750000 {
12 clock-frequency = <12750000>;
13 nvidia,parent-clock-frequency = <408000000>;
15 clock-names = "emc-parent";
18 timing-20400000 {
19 clock-frequency = <20400000>;
[all …]
Dtegra30-ouya.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-opp.dtsi"
10 #include "tegra30-cpu-opp-microvolt.dtsi"
26 stdout-path = "serial0:115200n8";
33 reserved-memory {
34 #address-cells = <1>;
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra30-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
30 Global Resources, which include things like configuration registers which
39 const: nvidia,tegra30-mc
47 clock-names:
[all …]
Dnvidia,tegra124-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
22 const: nvidia,tegra124-mc
30 clock-names:
32 - const: mc
[all …]
/Linux-v6.1/drivers/memory/tegra/
Dmc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
25 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
28 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
31 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
34 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
37 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
40 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
43 { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc },
46 { .compatible = "nvidia,tegra194-mc", .data = &tegra194_mc_soc },
[all …]
Dtegra30.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/memory/tegra30-mc.h>
1224 unsigned int fifo_size = client->fifo_size; in tegra30_mc_tune_client_latency()
1227 /* see 18.4.1 Client Configuration in Tegra3 TRM v03p */ in tegra30_mc_tune_client_latency()
1244 switch (client->swgroup) { in tegra30_mc_tune_client_latency()
1271 arb_nsec -= arb_tolerance_compensation_nsec; in tegra30_mc_tune_client_latency()
1279 * client may wait in the EMEM arbiter before it becomes a high-priority in tegra30_mc_tune_client_latency()
1282 la_ticks = arb_nsec / mc->tick; in tegra30_mc_tune_client_latency()
1283 la_ticks = min(la_ticks, client->regs.la.mask); in tegra30_mc_tune_client_latency()
1285 value = mc_readl(mc, client->regs.la.reg); in tegra30_mc_tune_client_latency()
[all …]
/Linux-v6.1/drivers/net/wireless/realtek/rtw88/
Drtw8822c.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
29 ether_addr_copy(efuse->addr, map->e.mac_addr); in rtw8822ce_efuse_parsing()
34 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8822c_read_efuse()
40 efuse->rfe_option = map->rfe_option; in rtw8822c_read_efuse()
41 efuse->rf_board_option = map->rf_board_option; in rtw8822c_read_efuse()
42 efuse->crystal_cap = map->xtal_k & XCAP_MASK; in rtw8822c_read_efuse()
43 efuse->channel_plan = map->channel_plan; in rtw8822c_read_efuse()
44 efuse->country_code[0] = map->country_code[0]; in rtw8822c_read_efuse()
45 efuse->country_code[1] = map->country_code[1]; in rtw8822c_read_efuse()
[all …]