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/Linux-v5.10/Documentation/devicetree/bindings/nvmem/
Drockchip-efuse.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/nvmem/rockchip-efuse.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip eFuse device tree bindings
10 - Heiko Stuebner <heiko@sntech.de>
13 - $ref: "nvmem.yaml#"
18 - rockchip,rk3066a-efuse
19 - rockchip,rk3188-efuse
20 - rockchip,rk3228-efuse
[all …]
Dsc27xx-efuse.txt1 = Spreadtrum SC27XX PMIC eFuse device tree bindings =
4 - compatible: Should be one of the following.
5 "sprd,sc2720-efuse"
6 "sprd,sc2721-efuse"
7 "sprd,sc2723-efuse"
8 "sprd,sc2730-efuse"
9 "sprd,sc2731-efuse"
10 - reg: Specify the address offset of efuse controller.
11 - hwlocks: Reference to a phandle of a hwlock provider node.
14 Are child nodes of eFuse, bindings of which as described in
[all …]
Duniphier-efuse.txt1 = UniPhier eFuse device tree bindings =
3 This UniPhier eFuse must be under soc-glue.
6 - compatible: should be "socionext,uniphier-efuse"
7 - reg: should contain the register location and length
10 Are child nodes of efuse, bindings of which as described in
15 soc-glue@5f900000 {
16 compatible = "socionext,uniphier-ld20-soc-glue-debug",
17 "simple-mfd";
18 #address-cells = <1>;
19 #size-cells = <1>;
[all …]
Dmtk-efuse.txt1 = Mediatek MTK-EFUSE device tree bindings =
3 This binding is intended to represent MTK-EFUSE which is found in most Mediatek SOCs.
6 - compatible: should be
7 "mediatek,mt7622-efuse", "mediatek,efuse": for MT7622
8 "mediatek,mt7623-efuse", "mediatek,efuse": for MT7623
9 "mediatek,mt8173-efuse" or "mediatek,efuse": for MT8173
10 - reg: Should contain registers location and length
13 Are child nodes of MTK-EFUSE, bindings of which as described in
18 efuse: efuse@10206000 {
19 compatible = "mediatek,mt8173-efuse";
[all …]
Damlogic-meson-mx-efuse.txt1 Amlogic Meson6/Meson8/Meson8b efuse
4 - compatible: depending on the SoC this should be one of:
5 - "amlogic,meson6-efuse"
6 - "amlogic,meson8-efuse"
7 - "amlogic,meson8b-efuse"
8 - reg: base address and size of the efuse registers
9 - clocks: a reference to the efuse core gate clock
10 - clock-names: must be "core"
12 All properties and sub-nodes as well as the consumer bindings
17 efuse: nvmem@0 {
[all …]
Damlogic-efuse.txt1 = Amlogic Meson GX eFuse device tree bindings =
4 - compatible: should be "amlogic,meson-gxbb-efuse"
5 - clocks: phandle to the efuse peripheral clock provided by the
7 - secure-monitor: phandle to the secure-monitor node
10 Are child nodes of eFuse, bindings of which as described in
15 efuse: efuse {
16 compatible = "amlogic,meson-gxbb-efuse";
18 #address-cells = <1>;
19 #size-cells = <1>;
20 secure-monitor = <&sm>;
[all …]
Dqcom,qfprom.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies Inc, QFPROM Efuse bindings
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 - $ref: "nvmem.yaml#"
20 # If the QFPROM is read-only OS image then only the corrected region
24 - items:
25 - description: The corrected region.
26 - items:
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/regulator/
Dti-abb-regulator.txt4 - compatible: Should be one of:
5 - "ti,abb-v1" for older SoCs like OMAP3
6 - "ti,abb-v2" for newer SoCs like OMAP4, OMAP5
7 - "ti,abb-v3" for a generic definition where setup and control registers are
9 - reg: Address and length of the register set for the device. It contains
10 the information of registers in the same order as described by reg-names
11 - reg-names: Should contain the reg names
12 - "base-address" - contains base address of ABB module (ti,abb-v1,ti,abb-v2)
13 - "control-address" - contains control register address of ABB module (ti,abb-v3)
14 - "setup-address" - contains setup register address of ABB module (ti,abb-v3)
[all …]
/Linux-v5.10/drivers/nvmem/
Drockchip-efuse.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip eFuse Driver
6 * Author: Caesar Wang <wxt@rock-chips.com>
14 #include <linux/nvmem-provider.h>
58 struct rockchip_efuse_chip *efuse = context; in rockchip_rk3288_efuse_read() local
62 ret = clk_prepare_enable(efuse->clk); in rockchip_rk3288_efuse_read()
64 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n"); in rockchip_rk3288_efuse_read()
68 writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
70 while (bytes--) { in rockchip_rk3288_efuse_read()
71 writel(readl(efuse->base + REG_EFUSE_CTRL) & in rockchip_rk3288_efuse_read()
[all …]
Dmeson-mx-efuse.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Amlogic Meson6, Meson8 and Meson8b eFuse Driver
15 #include <linux/nvmem-provider.h>
51 static void meson_mx_efuse_mask_bits(struct meson_mx_efuse *efuse, u32 reg, in meson_mx_efuse_mask_bits() argument
56 data = readl(efuse->base + reg); in meson_mx_efuse_mask_bits()
60 writel(data, efuse->base + reg); in meson_mx_efuse_mask_bits()
63 static int meson_mx_efuse_hw_enable(struct meson_mx_efuse *efuse) in meson_mx_efuse_hw_enable() argument
67 err = clk_prepare_enable(efuse->core_clk); in meson_mx_efuse_hw_enable()
71 /* power up the efuse */ in meson_mx_efuse_hw_enable()
72 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_hw_enable()
[all …]
Dsc27xx-efuse.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/nvmem-provider.h>
17 /* Efuse controller registers definition */
80 * On Spreadtrum platform, we have multi-subsystems will access the unique
81 * efuse controller, so we need one hardware spinlock to synchronize between
84 static int sc27xx_efuse_lock(struct sc27xx_efuse *efuse) in sc27xx_efuse_lock() argument
88 mutex_lock(&efuse->mutex); in sc27xx_efuse_lock()
90 ret = hwspin_lock_timeout_raw(efuse->hwlock, in sc27xx_efuse_lock()
93 dev_err(efuse->dev, "timeout to get the hwspinlock\n"); in sc27xx_efuse_lock()
94 mutex_unlock(&efuse->mutex); in sc27xx_efuse_lock()
[all …]
Djz4780-efuse.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * JZ4780 EFUSE Memory Support driver
10 * Currently supports JZ4780 efuse which has 8K programmable bit.
11 * Efuse is separated into seven segments as below:
13 * -----------------------------------------------------------------------
15 * -----------------------------------------------------------------------
27 #include <linux/nvmem-provider.h>
72 struct jz4780_efuse *efuse = context; in jz4780_efuse_read() local
75 size_t start = offset & ~(JZ_EFU_READ_SIZE - 1); in jz4780_efuse_read()
77 - offset); in jz4780_efuse_read()
[all …]
Dsprd-efuse.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/nvmem-provider.h>
39 * The Spreadtrum AP efuse contains 2 parts: normal efuse and secure efuse,
40 * and we can only access the normal efuse in kernel. So define the normal
52 * when reading or writing data to efuse memory, the controller can save double
79 * On Spreadtrum platform, we have multi-subsystems will access the unique
80 * efuse controller, so we need one hardware spinlock to synchronize between
83 static int sprd_efuse_lock(struct sprd_efuse *efuse) in sprd_efuse_lock() argument
87 mutex_lock(&efuse->mutex); in sprd_efuse_lock()
89 ret = hwspin_lock_timeout_raw(efuse->hwlock, in sprd_efuse_lock()
[all …]
Dmeson-efuse.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Amlogic Meson GX eFuse Driver
11 #include <linux/nvmem-provider.h>
36 { .compatible = "amlogic,meson-gxbb-efuse", },
43 struct device *dev = &pdev->dev; in meson_efuse_probe()
49 unsigned int size; in meson_efuse_probe() local
52 sm_np = of_parse_phandle(pdev->dev.of_node, "secure-monitor", 0); in meson_efuse_probe()
54 dev_err(&pdev->dev, "no secure-monitor node\n"); in meson_efuse_probe()
55 return -ENODEV; in meson_efuse_probe()
61 return -EPROBE_DEFER; in meson_efuse_probe()
[all …]
Dmtk-efuse.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
11 #include <linux/nvmem-provider.h>
25 while (words--) in mtk_reg_read()
26 *val++ = readl(priv->base + reg + (i++ * 4)); in mtk_reg_read()
33 struct device *dev = &pdev->dev; in mtk_efuse_probe()
41 return -ENOMEM; in mtk_efuse_probe()
44 priv->base = devm_ioremap_resource(dev, res); in mtk_efuse_probe()
45 if (IS_ERR(priv->base)) in mtk_efuse_probe()
46 return PTR_ERR(priv->base); in mtk_efuse_probe()
[all …]
Duniphier-efuse.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * UniPhier eFuse driver
12 #include <linux/nvmem-provider.h>
27 *val++ = readb(priv->base + reg + offs); in uniphier_reg_read()
34 struct device *dev = &pdev->dev; in uniphier_efuse_probe()
42 return -ENOMEM; in uniphier_efuse_probe()
45 priv->base = devm_ioremap_resource(dev, res); in uniphier_efuse_probe()
46 if (IS_ERR(priv->base)) in uniphier_efuse_probe()
47 return PTR_ERR(priv->base); in uniphier_efuse_probe()
53 econfig.size = resource_size(res); in uniphier_efuse_probe()
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/fuse/
Dnvidia,tegra20-fuse.txt4 - compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30,
5 must contain "nvidia,tegra30-efuse". For Tegra114, must contain
6 "nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse".
7 For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse".
8 For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain
9 "nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse".
10 For Tegra234 must contain "nvidia,tegra234-efuse".
12 nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
15 nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse:
16 The differences between these SoCs are the size of the efuse array,
[all …]
/Linux-v5.10/drivers/net/wireless/realtek/rtw88/
Defuse.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
8 #include "efuse.h"
31 /* efuse header format
37 * word_en: 4 bits each word. 0 -> write; 1 -> not write
43 u32 physical_size = rtwdev->efuse.physical_size; in rtw_dump_logical_efuse_map()
44 u32 protect_size = rtwdev->efuse.protect_size; in rtw_dump_logical_efuse_map()
45 u32 logical_size = rtwdev->efuse.logical_size; in rtw_dump_logical_efuse_map()
52 for (phy_idx = 0; phy_idx < physical_size - protect_size;) { in rtw_dump_logical_efuse_map()
59 /* 2-byte header format */ in rtw_dump_logical_efuse_map()
[all …]
Dphy.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
83 .size = ARRAY_SIZE(name), \
98 .size = ARRAY_SIZE(name), \
105 .size = ARRAY_SIZE(name), \
111 struct rtw_chip_info *chip = rtwdev->chip; in rtw_get_rfe_def()
112 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw_get_rfe_def() local
115 if (chip->rfe_defs_size == 0) in rtw_get_rfe_def()
118 if (efuse->rfe_option < chip->rfe_defs_size) in rtw_get_rfe_def()
119 rfe_def = &chip->rfe_defs[efuse->rfe_option]; in rtw_get_rfe_def()
[all …]
Dmain.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
14 #include "efuse.h"
126 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4,
139 struct rtw_bf_info *bf_info = &rtwdev->bf_info; in rtw_dynamic_csi_rate()
143 if (rtwvif->bfee.role != RTW_BFEE_SU && in rtw_dynamic_csi_rate()
144 rtwvif->bfee.role != RTW_BFEE_MU) in rtw_dynamic_csi_rate()
147 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi, in rtw_dynamic_csi_rate()
148 bf_info->cur_csi_rpt_rate, in rtw_dynamic_csi_rate()
151 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) in rtw_dynamic_csi_rate()
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/net/
Dkeystone-netcp.txt6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
[all …]
/Linux-v5.10/drivers/net/wireless/mediatek/mt76/mt7603/
Deeprom.c1 // SPDX-License-Identifier: ISC
21 return -ETIMEDOUT; in mt7603_efuse_read()
51 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, len, GFP_KERNEL); in mt7603_efuse_init()
52 dev->mt76.otp.size = len; in mt7603_efuse_init()
53 if (!dev->mt76.otp.data) in mt7603_efuse_init()
54 return -ENOMEM; in mt7603_efuse_init()
56 buf = dev->mt76.otp.data; in mt7603_efuse_init()
67 mt7603_has_cal_free_data(struct mt7603_dev *dev, u8 *efuse) in mt7603_has_cal_free_data() argument
69 if (!efuse[MT_EE_TEMP_SENSOR_CAL]) in mt7603_has_cal_free_data()
72 if (get_unaligned_le16(efuse + MT_EE_TX_POWER_0_START_2G) == 0) in mt7603_has_cal_free_data()
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/phy/
Dphy-mtk-xsphy.txt1 MediaTek XS-PHY binding
2 --------------------------
4 The XS-PHY controller supports physical layer functionality for USB3.1
8 - compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy",
9 soc-model is the name of SoC, such as mt3611 etc;
12 - "mediatek,mt3611-xsphy"
14 - #address-cells, #size-cells : should use the same values as the root node
15 - ranges: must be present
18 - reg : offset and length of register shared by multiple U3 ports,
21 - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/edac/
Dapm-xgene-edac.txt1 * APM X-Gene SoC EDAC node
3 EDAC node is defined to describe on-chip error detection and correction.
6 memory controller - Memory controller
7 PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
8 L3 - L3 cache controller
9 SoC - SoC IP's such as Ethernet, SATA, and etc
14 - compatible : Shall be "apm,xgene-edac".
15 - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
16 - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
17 - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Duniphier-pro5.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
9 compatible = "socionext,uniphier-pro5";
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
22 enable-method = "psci";
23 next-level-cache = <&l2>;
[all …]

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