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/Linux-v5.15/drivers/gpio/
Dgpio-rda.c1 // SPDX-License-Identifier: GPL-2.0-only
45 static inline void rda_gpio_update(struct gpio_chip *chip, unsigned int offset, in rda_gpio_update() argument
49 void __iomem *base = rda_gpio->base; in rda_gpio_update()
53 spin_lock_irqsave(&rda_gpio->lock, flags); in rda_gpio_update()
57 tmp |= BIT(offset); in rda_gpio_update()
59 tmp &= ~BIT(offset); in rda_gpio_update()
62 spin_unlock_irqrestore(&rda_gpio->lock, flags); in rda_gpio_update()
69 void __iomem *base = rda_gpio->base; in rda_gpio_irq_mask()
70 u32 offset = irqd_to_hwirq(data); in rda_gpio_irq_mask() local
73 value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT; in rda_gpio_irq_mask()
[all …]
Dgpio-sa1100.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-sa1100/gpio.c
5 * Generic SA-1100 GPIO handling
39 static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset) in sa1100_gpio_get() argument
41 return readl_relaxed(sa1100_gpio_chip(chip)->membase + R_GPLR) & in sa1100_gpio_get()
42 BIT(offset); in sa1100_gpio_get()
45 static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value) in sa1100_gpio_set() argument
49 writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg); in sa1100_gpio_set()
52 static int sa1100_get_direction(struct gpio_chip *chip, unsigned offset) in sa1100_get_direction() argument
54 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; in sa1100_get_direction()
[all …]
Dgpio-pl061.c1 // SPDX-License-Identifier: GPL-2.0-only
63 static int pl061_get_direction(struct gpio_chip *gc, unsigned offset) in pl061_get_direction() argument
67 if (readb(pl061->base + GPIODIR) & BIT(offset)) in pl061_get_direction()
73 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) in pl061_direction_input() argument
79 raw_spin_lock_irqsave(&pl061->lock, flags); in pl061_direction_input()
80 gpiodir = readb(pl061->base + GPIODIR); in pl061_direction_input()
81 gpiodir &= ~(BIT(offset)); in pl061_direction_input()
82 writeb(gpiodir, pl061->base + GPIODIR); in pl061_direction_input()
83 raw_spin_unlock_irqrestore(&pl061->lock, flags); in pl061_direction_input()
88 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset, in pl061_direction_output() argument
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Dgpio-mxs.c1 // SPDX-License-Identifier: GPL-2.0+
7 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
26 #define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
27 #define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
28 #define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
29 #define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
30 #define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
31 #define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
32 #define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
33 #define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
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Dgpio-stmpe.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2010
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
41 static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset) in stmpe_gpio_get() argument
44 struct stmpe *stmpe = stmpe_gpio->stmpe; in stmpe_gpio_get()
45 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)]; in stmpe_gpio_get()
46 u8 mask = BIT(offset % 8); in stmpe_gpio_get()
56 static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val) in stmpe_gpio_set() argument
59 struct stmpe *stmpe = stmpe_gpio->stmpe; in stmpe_gpio_set()
61 u8 reg = stmpe->regs[which + (offset / 8)]; in stmpe_gpio_set()
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Dgpio-rcar.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas R-Car GPIO Support
63 #define EDGLEVEL 0x24 /* Edge/level Select Register */
66 #define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
73 return ioread32(p->base + offs); in gpio_rcar_read()
79 iowrite32(value, p->base + offs); in gpio_rcar_write()
120 * "Setting Edge-Sensitive Interrupt Input Mode" and in gpio_rcar_config_interrupt_input_mode()
121 * "Setting Level-Sensitive Interrupt Input Mode" in gpio_rcar_config_interrupt_input_mode()
124 spin_lock_irqsave(&p->lock, flags); in gpio_rcar_config_interrupt_input_mode()
129 /* Configure edge or level trigger in EDGLEVEL */ in gpio_rcar_config_interrupt_input_mode()
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Dgpio-grgpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 * See "Documentation/devicetree/bindings/gpio/gpio-grgpio.txt" for
45 /* Structure for an irq of the core - called an underlying irq */
56 s8 index; /* Index into struct grgpio_priv's uirqs, or -1 */
83 * obtains from this driver. An index value of -1 for a certain gpio
90 static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset, in grgpio_set_imask() argument
93 struct gpio_chip *gc = &priv->gc; in grgpio_set_imask()
96 priv->imask |= BIT(offset); in grgpio_set_imask()
98 priv->imask &= ~BIT(offset); in grgpio_set_imask()
99 gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask); in grgpio_set_imask()
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Dgpio-mvebu.c6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
22 * - the basic variant, called "orion-gpio", with the simplest
24 * non-SMP Discovery systems
25 * - the mv78200 variant for MV78200 Discovery systems. This variant
26 * turns the edge mask and level mask registers into CPU0 edge
27 * mask/level mask registers, and adds CPU1 edge mask/level mask
29 * - the armadaxp variant for Armada XP systems. This variant keeps
30 * the normal cause/edge mask/level mask registers when the global
31 * interrupts are used, but adds per-CPU cause/edge mask/level mask
[all …]
Dgpio-omap.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2003-2005 Nokia Corporation
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
27 #include <linux/platform_data/gpio-omap.h>
83 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
84 #define LINE_USED(line, offset) (line & (BIT(offset))) argument
111 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction()
117 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, in omap_set_gpio_dataout_reg() argument
120 void __iomem *reg = bank->base; in omap_set_gpio_dataout_reg()
121 u32 l = BIT(offset); in omap_set_gpio_dataout_reg()
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Dgpio-mxc.c1 // SPDX-License-Identifier: GPL-2.0+
8 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
75 .edge_sel_reg = -EINVAL,
90 .edge_sel_reg = -EINVAL,
112 #define GPIO_DR (port->hwdata->dr_reg)
113 #define GPIO_GDIR (port->hwdata->gdir_reg)
114 #define GPIO_PSR (port->hwdata->psr_reg)
115 #define GPIO_ICR1 (port->hwdata->icr1_reg)
116 #define GPIO_ICR2 (port->hwdata->icr2_reg)
117 #define GPIO_IMR (port->hwdata->imr_reg)
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/Linux-v5.15/fs/btrfs/
Dbackref.c1 // SPDX-License-Identifier: GPL-2.0
10 #include "disk-io.h"
14 #include "delayed-ref.h"
17 #include "tree-mod-log.h"
24 u64 offset; member
35 u64 offset = 0; in check_extent_in_eb() local
51 offset = extent_item_pos - data_offset; in check_extent_in_eb()
56 return -ENOMEM; in check_extent_in_eb()
58 e->next = *eie; in check_extent_in_eb()
59 e->inum = key->objectid; in check_extent_in_eb()
[all …]
Drelocation.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/error-injection.h>
14 #include "disk-io.h"
19 #include "async-thread.h"
20 #include "free-space-cache.h"
22 #include "print-tree.h"
23 #include "delalloc-space.h"
24 #include "block-group.h"
40 * ------------------------------------------------------------------
47 * 1. Mark the target block group read-only
[all …]
Dbackref.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include "disk-io.h"
20 typedef int (iterate_extent_inodes_t)(u64 inum, u64 offset, u64 root,
105 btrfs_free_path(iter->path); in btrfs_backref_iter_free()
114 return iter->path->nodes[0]; in btrfs_backref_get_eb()
118 * For metadata with EXTENT_ITEM key (non-skinny) case, the first inline data
126 if (iter->cur_key.type == BTRFS_EXTENT_ITEM_KEY && in btrfs_backref_has_tree_block_info()
127 iter->cur_ptr - iter->item_ptr == sizeof(struct btrfs_extent_item)) in btrfs_backref_has_tree_block_info()
139 if (iter->cur_key.type == BTRFS_EXTENT_ITEM_KEY || in btrfs_backref_iter_is_inline_ref()
140 iter->cur_key.type == BTRFS_METADATA_ITEM_KEY) in btrfs_backref_iter_is_inline_ref()
[all …]
/Linux-v5.15/drivers/gpu/drm/ast/
Dast_dp501.c1 // SPDX-License-Identifier: GPL-2.0
15 release_firmware(ast->dp501_fw); in ast_release_firmware()
16 ast->dp501_fw = NULL; in ast_release_firmware()
24 ret = request_firmware(&ast->dp501_fw, "ast_dp501_fw.bin", dev->dev); in ast_load_dp501_microcode()
28 return devm_add_action_or_reset(dev->dev, ast_release_firmware, ast); in ast_load_dp501_microcode()
192 if (ast->config_mode != ast_use_p2a) in ast_backup_fw()
213 if (ast->config_mode != ast_use_p2a) in ast_launch_m68k()
219 if (ast->dp501_fw_addr) { in ast_launch_m68k()
220 fw_addr = ast->dp501_fw_addr; in ast_launch_m68k()
223 if (!ast->dp501_fw && in ast_launch_m68k()
[all …]
/Linux-v5.15/drivers/media/rc/
Dserial_ir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * serial_ir - Device driver that records pulse- and pause-lengths
6 * (space-lengths) between DDCD event on a serial port.
8 * Copyright (C) 1996,97 Ralph Metzler <rjkm@thp.uni-koeln.de>
13 * Copyright (C) 2016 Sean Young <sean@mess.org> (port to rc-core)
27 #include <media/rc-core.h>
36 void (*send_pulse)(unsigned int length, ktime_t edge);
55 static int sense = -1; /* -1 = auto, 0 = active high, 1 = active low */
59 static void send_pulse_irdeo(unsigned int length, ktime_t edge);
62 static void send_pulse_homebrew(unsigned int length, ktime_t edge);
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/Linux-v5.15/drivers/pinctrl/
Dpinctrl-at91.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Parallel I/O Controller (PIO) - System peripherals registers.
29 #define PIO_MDER 0x50 /* Multi-driver Enable Register */
30 #define PIO_MDDR 0x54 /* Multi-driver Disable Register */
31 #define PIO_MDSR 0x58 /* Multi-driver Status Register */
32 #define PIO_PUDR 0x60 /* Pull-up Disable Register */
33 #define PIO_PUER 0x64 /* Pull-up Enable Register */
34 #define PIO_PUSR 0x68 /* Pull-up Status Register */
45 #define PIO_PPDDR 0x90 /* Pad Pull-down Disable Register */
46 #define PIO_PPDER 0x94 /* Pad Pull-down Enable Register */
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/Linux-v5.15/Documentation/virt/kvm/devices/
Dmpic.rst1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_FSL_MPIC_20 Freescale MPIC v2.0
10 - KVM_DEV_TYPE_FSL_MPIC_42 Freescale MPIC v4.2
20 KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
25 KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)
27 "attr" is the byte offset into the MPIC register space. Accesses
28 must be 4-byte aligned.
33 KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)
37 For edge-triggered interrupts: Writing 1 is considered an activating
38 edge, and writing 0 is ignored. Reading returns 1 if a previously
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/Linux-v5.15/arch/mips/lantiq/
Dirq.c1 // SPDX-License-Identifier: GPL-2.0-only
23 /* register definitions - internal irqs */
32 /* register definitions - external irqs */
75 return -1; in ltq_eiu_get_irq()
80 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; in ltq_disable_irq() local
81 unsigned long im = offset / INT_NUM_IM_OFFSET; in ltq_disable_irq()
85 offset %= INT_NUM_IM_OFFSET; in ltq_disable_irq()
90 ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset), in ltq_disable_irq()
98 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; in ltq_mask_and_ack_irq() local
99 unsigned long im = offset / INT_NUM_IM_OFFSET; in ltq_mask_and_ack_irq()
[all …]
/Linux-v5.15/drivers/pinctrl/qcom/
Dpinctrl-msm.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/pinctrl/pinconf-generic.h>
31 #include "pinctrl-msm.h"
32 #include "../pinctrl-utils.h"
39 * struct msm_pinctrl - state for a pinctrl-msm device
51 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
87 return readl(pctrl->regs[g->tile] + g->name##_reg); \
92 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
104 u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0; in MSM_ACCESSOR()
113 return pctrl->soc->ngroups; in msm_get_groups_count()
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/Linux-v5.15/Documentation/devicetree/bindings/soc/qcom/
Dqcom,smd.txt7 - compatible:
15 processor of some sort - or in SMD language an "edge". The name of the edges
17 The edge is described by the following properties:
19 - interrupts:
21 Value type: <prop-encoded-array>
25 - mboxes:
27 Value type: <prop-encoded-array>
31 - qcom,ipc:
33 Value type: <prop-encoded-array>
36 - phandle to a syscon node representing the apcs registers
[all …]
Dqcom,smp2p.txt4 a single 32-bit value between two processors. Each value has a single writer
6 identified in the system by the directed edge (local processor ID to remote
9 - compatible:
15 - interrupts:
17 Value type: <prop-encoded-array>
20 - mboxes:
22 Value type: <prop-encoded-array>
26 - qcom,ipc:
28 Value type: <prop-encoded-array>
30 signaling the remote end of the smp2p edge:
[all …]
/Linux-v5.15/drivers/mfd/
Dasic3.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright 2004-2005 Phil Blundell
9 * Copyright 2007-2008 OpenedHand Ltd.
88 static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
92 iowrite16(value, asic->mapping + in asic3_write_register()
93 (reg >> asic->bus_shift)); in asic3_write_register()
99 return ioread16(asic->mapping + in asic3_read_register()
100 (reg >> asic->bus_shift)); in asic3_read_register()
109 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_set_register()
116 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_set_register()
[all …]
/Linux-v5.15/arch/arm/plat-pxa/
Dmfp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/plat-pxa/mfp.c
5 * Multi-Function Pin Support
9 * 2007-08-21: eric miao <eric.miao@marvell.com>
43 * used in parentheses for don't-care values. Except for the float output,
45 * non-LPM pulled output, the same configuration could probably be used.
85 * (most likely a read-modify-write operation) is atomic, and that
93 unsigned long config; /* -1 for not configured */
94 unsigned long mfpr_off; /* MFPRxx Register offset */
95 unsigned long mfpr_run; /* Run-Mode Register Value */
[all …]
/Linux-v5.15/drivers/gpu/drm/sti/
Dsti_vtg.c1 // SPDX-License-Identifier: GPL-2.0
24 /* registers offset */
74 #define AWG_DELAY_HD (-9)
75 #define AWG_DELAY_ED (-8)
76 #define AWG_DELAY_SD (-7)
79 * STI VTG register offset structure
81 *@h_hd: stores the VTG_H_HD_x register offset
82 *@top_v_vd: stores the VTG_TOP_V_VD_x register offset
83 *@bot_v_vd: stores the VTG_BOT_V_VD_x register offset
84 *@top_v_hd: stores the VTG_TOP_V_HD_x register offset
[all …]
/Linux-v5.15/arch/arm/mach-omap1/
Dams-delta-fiq.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * Parts of this code are taken from linux/arch/arm/mach-omap/irq.c
20 #include <linux/platform_data/ams-delta-fiq.h>
25 #include "ams-delta-fiq.h"
26 #include "board-ams-delta.h"
29 .name = "ams-delta-fiq"
38 * <linux/platform_data/ams-delta-fiq.h> for details of offsets.
63 irq_num = d->irq; in deferred_fiq()
69 * handle_simple_irq() that OMAP GPIO edge in deferred_fiq()
73 if (!WARN_ON_ONCE(!irq_chip->irq_unmask)) in deferred_fiq()
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