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/Linux-v5.15/Documentation/devicetree/bindings/mmc/
Dfsl-esdhc.txt1 * Freescale Enhanced Secure Digital Host Controller (eSDHC)
7 by mmc.txt and the properties used by the sdhci-esdhc driver.
10 - compatible : should be "fsl,esdhc", or "fsl,<chip>-esdhc".
12 "fsl,mpc8536-esdhc"
13 "fsl,mpc8378-esdhc"
14 "fsl,p2020-esdhc"
15 "fsl,p4080-esdhc"
16 "fsl,t1040-esdhc"
17 "fsl,t4240-esdhc"
19 "fsl,ls1012a-esdhc"
[all …]
Dfsl-imx-esdhc.yaml4 $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
7 title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
26 - fsl,imx25-esdhc
27 - fsl,imx35-esdhc
28 - fsl,imx51-esdhc
29 - fsl,imx53-esdhc
64 due to signal path is too long on the board. Please refer to eSDHC/uSDHC
141 compatible = "fsl,imx51-esdhc";
148 compatible = "fsl,imx51-esdhc";
/Linux-v5.15/drivers/mmc/host/
Dsdhci-of-esdhc.c3 * Freescale eSDHC controller driver.
27 #include "sdhci-esdhc.h"
65 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
66 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
67 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
68 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk},
69 { .compatible = "fsl,mpc8379-esdhc" },
70 { .compatible = "fsl,mpc8536-esdhc" },
71 { .compatible = "fsl,esdhc" },
94 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
[all …]
Dsdhci-esdhc-mcf.c3 * Freescale eSDHC ColdFire family controller driver, platform bus.
11 #include <linux/platform_data/mmc-esdhc-mcf.h>
14 #include "sdhci-esdhc.h"
21 * Freescale eSDHC has DMA ERR flag at bit 28, not as std spec says, bit 25.
235 * ColdFire eSDHC clock.s in esdhc_mcf_pltfm_set_clock()
238 * +-> / outdiv3 --> eSDHC clock ---> / SDCCLKFS / DVS in esdhc_mcf_pltfm_set_clock()
241 * (8.1.2) eSDHC should be 40 MHz max in esdhc_mcf_pltfm_set_clock()
242 * (25.3.9) eSDHC input is, as example, 96 Mhz ... in esdhc_mcf_pltfm_set_clock()
511 .name = "sdhci-esdhc-mcf",
520 MODULE_DESCRIPTION("SDHCI driver for Freescale ColdFire eSDHC");
Dsdhci-pltfm.c66 if (of_device_is_compatible(np, "fsl,p2020-rev1-esdhc")) in sdhci_get_compatibility()
69 if (of_device_is_compatible(np, "fsl,p2020-esdhc") || in sdhci_get_compatibility()
70 of_device_is_compatible(np, "fsl,p1010-esdhc") || in sdhci_get_compatibility()
71 of_device_is_compatible(np, "fsl,t4240-esdhc") || in sdhci_get_compatibility()
72 of_device_is_compatible(np, "fsl,mpc8536-esdhc")) in sdhci_get_compatibility()
Dsdhci-esdhc.h3 * Freescale eSDHC controller driver generics for OF and pltfm.
16 * Ops and quirks for the Freescale eSDHC controller.
30 * eSDHC register definition
Dsdhci-esdhc-imx.c3 * Freescale eSDHC i.MX controller driver for the platform bus.
29 #include "sdhci-esdhc.h"
125 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
126 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
127 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
128 * Define this macro DMA error INT for fsl eSDHC
148 * The flag tells that the ESDHC controller is an USDHC block that is
213 * struct esdhc_platform_data - platform data for esdhc on i.MX
337 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
338 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
[all …]
DMakefile82 obj-$(CONFIG_MMC_SDHCI_ESDHC_MCF) += sdhci-esdhc-mcf.o
83 obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o
89 obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
DKconfig193 tristate "SDHCI OF support for the Freescale eSDHC controller"
199 This selects the Freescale eSDHC controller support.
265 tristate "SDHCI support for the Freescale eSDHC ColdFire controller"
270 This selects the Freescale eSDHC controller support for
278 tristate "SDHCI support for the Freescale eSDHC/uSDHC i.MX controller"
285 This selects the Freescale eSDHC/uSDHC controller support
/Linux-v5.15/arch/arm/boot/dts/
Dimx50.dtsi119 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
131 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
180 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
192 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
Dimx35.dtsi235 compatible = "fsl,imx35-esdhc";
244 compatible = "fsl,imx35-esdhc";
253 compatible = "fsl,imx35-esdhc";
Dimx51.dtsi189 compatible = "fsl,imx51-esdhc";
200 compatible = "fsl,imx51-esdhc";
249 compatible = "fsl,imx51-esdhc";
261 compatible = "fsl,imx51-esdhc";
/Linux-v5.15/arch/powerpc/boot/dts/fsl/
Dpq3-esdhc-0.dtsi2 * PQ3 eSDHC device tree stub [ controller @ offset 0x2e000 ]
36 compatible = "fsl,esdhc";
Dqoriq-esdhc-0.dtsi2 * QorIQ eSDHC device tree stub [ controller @ offset 0x114000 ]
36 compatible = "fsl,esdhc";
Dc293si-post.dtsi113 /include/ "pq3-esdhc-0.dtsi"
115 compatible = "fsl,c293-esdhc", "fsl,esdhc";
Dp1020si-post.dtsi154 /include/ "pq3-esdhc-0.dtsi"
156 compatible = "fsl,p1020-esdhc", "fsl,esdhc";
Dp1010si-post.dtsi172 /include/ "pq3-esdhc-0.dtsi"
174 compatible = "fsl,p1010-esdhc", "fsl,esdhc";
Dp2020si-post.dtsi187 /include/ "pq3-esdhc-0.dtsi"
189 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
Dmpc8536si-post.dtsi238 /include/ "pq3-esdhc-0.dtsi"
240 compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
Dp1022si-post.dtsi215 /include/ "pq3-esdhc-0.dtsi"
217 compatible = "fsl,p1022-esdhc", "fsl,esdhc";
Dmvme2500.dts270 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
/Linux-v5.15/arch/arm64/boot/dts/freescale/
Dfsl-ls1012a.dtsi159 esdhc0: esdhc@1560000 {
160 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
178 esdhc1: esdhc@1580000 {
179 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
Dfsl-ls1028a-rdb.dts22 mmc0 = &esdhc;
105 &esdhc {
Dfsl-ls1028a-kontron-sl28.dts27 mmc1 = &esdhc;
101 &esdhc {
/Linux-v5.15/arch/m68k/coldfire/
Dm5441x.c56 DEFINE_CLK(0, "sdhci-esdhc-mcf.0", 51, MCF_CLK);
118 CLKDEV_INIT("sdhci-esdhc-mcf.0", NULL, &__clk_0_51),
161 &__clk_0_51, /* esdhc */
184 &__clk_0_51, /* eSDHC */

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