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/Linux-v6.6/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra186-display.yaml164 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
183 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
Dnvidia,tegra114-mipi.yaml73 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
/Linux-v6.6/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-pmc.yaml290 audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic,
296 debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi,
Dnvidia,tegra186-pmc.yaml89 hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib,
/Linux-v6.6/arch/arm/boot/dts/nvidia/
Dtegra114.dtsi130 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
137 dsib: dsi@54400000 { label
Dtegra114-asus-tf701t.dts65 nvidia,ganged-mode = <&dsib>;
Dtegra30-peripherals-opp.dtsi1114 dsib_dvfs_opp_table: opp-table-dsib {
/Linux-v6.6/arch/arm64/boot/dts/nvidia/
Dtegra210.dtsi203 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
218 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
232 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
259 dsib: dsi@54400000 { label
Dtegra186.dtsi1608 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1627 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1697 dsib: dsi@15400000 { label
/Linux-v6.6/drivers/soc/tegra/
Dpmc.c3513 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"),
3546 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"),
3648 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"),
3689 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"),
3785 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 8, 0x7c, 0x80, UINT_MAX, "dsib"),
3826 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"),
/Linux-v6.6/drivers/clk/tegra/
Dclk-tegra114.c1033 /* dsib mux */ in tegra114_periph_clk_init()
1044 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base, in tegra114_periph_clk_init()
Dclk-tegra124.c1048 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0, in tegra124_periph_clk_init()
1499 /* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */ in tegra124_132_clock_init_pre()
Dclk-tegra210.c3124 /* dsib */ in tegra210_periph_clk_init()
3125 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0, in tegra210_periph_clk_init()
3797 /* For Tegra210, PLLD is the only source for DSIA & DSIB */ in tegra210_clock_init()
Dclk-tegra30.c997 …TEGRA_INIT_DATA_NODIV("dsib", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, TEGRA30_CLK…