Home
last modified time | relevance | path

Searched +full:dsi +full:- +full:phy (Results 1 – 25 of 168) sorted by relevance

1234567

/Linux-v5.15/drivers/gpu/drm/rockchip/
Ddw-mipi-dsi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Chris Zhong <zyw@rock-chips.com>
6 * Nickey Yang <nickey.yang@rock-chips.com>
15 #include <linux/phy/phy.h>
17 #include <linux/phy/phy.h>
41 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
93 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
96 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
97 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
230 int (*dphy_rx_init)(struct phy *phy);
[all …]
/Linux-v5.15/drivers/gpu/drm/hisilicon/kirin/
Ddw_drm_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * DesignWare MIPI DSI Host Controller v1.02 driver
6 * Copyright (c) 2014-2016 HiSilicon Limited.
88 struct mipi_phy_params phy; member
97 struct dw_dsi dsi; member
121 static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy) in dsi_calc_phy_rate() argument
151 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M; in dsi_calc_phy_rate()
152 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel; in dsi_calc_phy_rate()
154 if (phy->hstx_ckg_sel <= 7 && in dsi_calc_phy_rate()
155 phy->hstx_ckg_sel >= 4) in dsi_calc_phy_rate()
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/display/msm/
Ddsi-phy-7nm.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI 7nm PHY
10 - Jonathan Marek <jonathan@marek.ca>
13 - $ref: dsi-phy-common.yaml#
18 - qcom,dsi-phy-7nm
19 - qcom,dsi-phy-7nm-8150
20 - qcom,sc7280-dsi-phy-7nm
[all …]
Ddsi-phy-28nm.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI 28nm PHY
10 - Krishna Manikandan <mkrishn@codeaurora.org>
13 - $ref: dsi-phy-common.yaml#
18 - qcom,dsi-phy-28nm-hpm
19 - qcom,dsi-phy-28nm-lp
20 - qcom,dsi-phy-28nm-8960
[all …]
Ddsi-phy-14nm.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI 14nm PHY
10 - Krishna Manikandan <mkrishn@codeaurora.org>
13 - $ref: dsi-phy-common.yaml#
18 - qcom,dsi-phy-14nm
19 - qcom,dsi-phy-14nm-660
23 - description: dsi phy register set
[all …]
Ddsi-phy-10nm.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI 10nm PHY
10 - Krishna Manikandan <mkrishn@codeaurora.org>
13 - $ref: dsi-phy-common.yaml#
18 - qcom,dsi-phy-10nm
19 - qcom,dsi-phy-10nm-8998
23 - description: dsi phy register set
[all …]
Ddsi-phy-20nm.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI 20nm PHY
10 - Krishna Manikandan <mkrishn@codeaurora.org>
13 - $ref: dsi-phy-common.yaml#
17 const: qcom,dsi-phy-20nm
21 - description: dsi pll register set
22 - description: dsi phy register set
[all …]
/Linux-v5.15/drivers/gpu/drm/msm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
73 bool "Enable DSI support in MSM DRM driver"
79 Choose this option if you have a need for MIPI DSI connector
83 bool "Enable DSI 28nm PHY driver in MSM DRM"
87 Choose this option if the 28nm DSI PHY is used on the platform.
90 bool "Enable DSI 20nm PHY driver in MSM DRM"
94 Choose this option if the 20nm DSI PHY is used on the platform.
97 bool "Enable DSI 28nm 8960 PHY driver in MSM DRM"
101 Choose this option if the 28nm DSI PHY 8960 variant is used on the
105 bool "Enable DSI 14nm PHY driver in MSM DRM (used by MSM8996/APQ8096)"
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 ccflags-y := -I $(srctree)/$(src)
3 ccflags-y += -I $(srctree)/$(src)/disp/dpu1
4 ccflags-$(CONFIG_DRM_MSM_DSI) += -I $(srctree)/$(src)/dsi
5 ccflags-$(CONFIG_DRM_MSM_DP) += -I $(srctree)/$(src)/dp
7 msm-y := \
102 msm-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \
105 msm-$(CONFIG_DRM_MSM_GPU_STATE) += adreno/a6xx_gpu_state.o
107 msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
119 msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
[all …]
/Linux-v5.15/drivers/phy/mediatek/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the phy drivers.
6 obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
7 obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
8 obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
10 phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
11 phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
12 phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt8173.o
13 obj-$(CONFIG_PHY_MTK_HDMI) += phy-mtk-hdmi-drv.o
15 phy-mtk-mipi-dsi-drv-y := phy-mtk-mipi-dsi.o
[all …]
/Linux-v5.15/drivers/gpu/drm/bridge/
Dnwl-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * i.MX8 NWL MIPI DSI host driver
18 #include <linux/phy/phy.h>
33 #include "nwl-dsi.h"
35 #define DRV_NAME "nwl-dsi"
70 struct phy *phy; member
77 * The DSI host controller needs this reset sequence according to NWL:
78 * 1. Deassert pclk reset to get access to DSI regs
79 * 2. Configure DSI Host and DPHY and enable DPHY
81 * 4. Send DSI cmds to configure peripheral (handled by panel drv)
[all …]
/Linux-v5.15/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy_10nm.c2 * SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
11 #include "dsi.xml.h"
15 * DSI PLL 10nm - clock diagram (eg: DSI0):
20 * +---------+ | +----------+ | +----+
21 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
22 * +---------+ | +----------+ | +----+
26 * | | +----+ | |\ dsi0_pclk_mux
27 * | |--| /2 |--o--| \ |
28 * | | +----+ | \ | +---------+
[all …]
Ddsi_phy_7nm.c2 * SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
11 #include "dsi.xml.h"
15 * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram
20 * +---------+ | +----------+ | +----+
21 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
22 * +---------+ | +----------+ | +----+
26 * | | +----+ | |\ dsi0_pclk_mux
27 * | |--| /2 |--o--| \ |
28 * | | +----+ | \ | +---------+
[all …]
Ddsi_phy_14nm.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include "dsi.xml.h"
17 * DSI PLL 14nm - clock diagram (eg: DSI0):
22 * +----+ | +----+
23 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
24 * +----+ | +----+
26 * | +----+ |
27 * o---| /2 |--o--|\
28 * | +----+ | \ +----+
[all …]
Ddsi_phy_28nm.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
10 #include "dsi.xml.h"
14 * DSI PLL 28nm - clock diagram (eg: DSI0):
19 * +------+ | +----+ | |\ dsi0byte_mux
20 * dsi0vco_clk --o--| DIV1 |--o--| /2 |--o--| \ |
21 * | +------+ +----+ | m| | +----+
22 * | | u|--o--| /4 |-- dsi0pllbyte
23 * | | x| +----+
24 * o--------------------------| /
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,dsi.txt1 Mediatek DSI Device
4 The Mediatek DSI function block is a sink of the display subsystem and can
5 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
9 - compatible: "mediatek,<chip>-dsi"
10 - the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
11 - reg: Physical base address and length of the controller's registers
12 - interrupts: The interrupt signal from the function block.
13 - clocks: device clocks
14 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
15 - clock-names: must contain "engine", "digital", and "hs"
[all …]
/Linux-v5.15/drivers/gpu/drm/msm/dsi/
Ddsi_manager.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "dsi.h"
22 struct msm_dsi *dsi[DSI_MAX]; member
37 return msm_dsim_glb.dsi[id]; in dsi_mgr_get_dsi()
42 return msm_dsim_glb.dsi[(id + 1) % DSI_MAX]; in dsi_mgr_get_other_dsi()
49 /* We assume 2 dsi nodes have the same information of bonded dsi and in dsi_mgr_parse_of()
50 * sync-mode, and only one node specifies master in case of bonded mode. in dsi_mgr_parse_of()
52 if (!msm_dsim->is_bonded_dsi) in dsi_mgr_parse_of()
53 msm_dsim->is_bonded_dsi = of_property_read_bool(np, "qcom,dual-dsi-mode"); in dsi_mgr_parse_of()
55 if (msm_dsim->is_bonded_dsi) { in dsi_mgr_parse_of()
[all …]
Ddsi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
36 /* Regulators for DSI devices */
54 /* internal dsi bridge attached to MDP interface */
58 struct msm_dsi_phy *phy; member
61 * panel/external_bridge connected to dsi bridge output, only one of the
70 /* the encoder we are hooked to (outside of dsi block) */
76 /* dsi manager */
88 /* msm dsi */
91 return msm_dsi->panel || msm_dsi->external_bridge; in msm_dsi_device_connected()
96 /* dsi host */
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/display/rockchip/
Ddw_mipi_dsi_rockchip.txt1 Rockchip specific extensions to the Synopsys Designware MIPI DSI
5 - #address-cells: Should be <1>.
6 - #size-cells: Should be <0>.
7 - compatible: one of
8 "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
9 "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
10 "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
11 - reg: Represent the physical address range of the controller.
12 - interrupts: Represent the controller's interrupt to the CPU(s).
13 - clocks, clock-names: Phandles to the controller's pll reference
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/display/bridge/
Dcdns,dsi.txt1 Cadence DSI bridge
4 The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.
7 - compatible: should be set to "cdns,dsi".
8 - reg: physical base address and length of the controller's registers.
9 - interrupts: interrupt line connected to the DSI bridge.
10 - clocks: DSI bridge clocks.
11 - clock-names: must contain "dsi_p_clk" and "dsi_sys_clk".
12 - phys: phandle link to the MIPI D-PHY controller.
13 - phy-names: must contain "dphy".
14 - #address-cells: must be set to 1.
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/display/exynos/
Dexynos_dsim.txt1 Exynos MIPI DSI Master
4 - compatible: value should be one of the following
5 "samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */
6 "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
7 "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
8 "samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
9 "samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
10 - reg: physical base address and length of the registers set for the device
11 - interrupts: should contain DSI interrupt
12 - clocks: list of clock specifiers, must contain an entry for each required
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/display/
Dbrcm,bcm2835-dsi0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/brcm,bcm2835-dsi0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom VC4 (VideoCore4) DSI Controller
10 - Eric Anholt <eric@anholt.net>
13 - $ref: dsi-controller.yaml#
16 "#clock-cells":
21 - brcm,bcm2711-dsi1
22 - brcm,bcm2835-dsi0
[all …]
Dallwinner,sun6i-a31-mipi-dsi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 MIPI-DSI Controller Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - allwinner,sun6i-a31-mipi-dsi
17 - allwinner,sun50i-a64-mipi-dsi
28 - description: Bus Clock
[all …]
/Linux-v5.15/drivers/gpu/drm/mediatek/
Dmtk_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/phy/phy.h>
173 struct phy;
188 struct phy *phy; member
220 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data) in mtk_dsi_mask() argument
222 u32 temp = readl(dsi->regs + offset); in mtk_dsi_mask()
224 writel((temp & ~mask) | (data & mask), dsi->regs + offset); in mtk_dsi_mask()
227 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) in mtk_dsi_phy_timconfig() argument
230 u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000); in mtk_dsi_phy_timconfig()
231 struct mtk_phy_timing *timing = &dsi->phy_timing; in mtk_dsi_phy_timconfig()
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/clock/
Dqcom,mmcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeffrey Hugo <jhugo@codeaurora.org>
11 - Taniya Das <tdas@codeaurora.org>
20 - qcom,mmcc-apq8064
21 - qcom,mmcc-apq8084
22 - qcom,mmcc-msm8660
23 - qcom,mmcc-msm8960
24 - qcom,mmcc-msm8974
[all …]

1234567