| /Linux-v5.10/drivers/net/wireless/intel/iwlwifi/pcie/ |
| D | ctxt-info.c | 98 struct iwl_dram_data *dram) in iwl_pcie_ctxt_info_alloc_dma() argument
100 dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent(trans, len, in iwl_pcie_ctxt_info_alloc_dma()
101 &dram->physical); in iwl_pcie_ctxt_info_alloc_dma()
102 if (!dram->block) in iwl_pcie_ctxt_info_alloc_dma()
105 dram->size = len; in iwl_pcie_ctxt_info_alloc_dma()
106 memcpy(dram->block, data, len); in iwl_pcie_ctxt_info_alloc_dma()
113 struct iwl_self_init_dram *dram = &trans->init_dram; in iwl_pcie_ctxt_info_free_paging() local
116 if (!dram->paging) { in iwl_pcie_ctxt_info_free_paging()
117 WARN_ON(dram->paging_cnt); in iwl_pcie_ctxt_info_free_paging()
122 for (i = 0; i < dram->paging_cnt; i++) in iwl_pcie_ctxt_info_free_paging()
[all …]
|
| /Linux-v5.10/Documentation/devicetree/bindings/devfreq/ |
| D | rk3399_dmc.txt | 41 clocks freq is half of DRAM clock), default
58 The controller, pi, PHY and DRAM clock will
72 - rockchip,ddr3_odt_dis_freq : When the DRAM type is DDR3, this parameter defines
75 the ODT on the DRAM side and controller side are
78 - rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines
79 the DRAM side driver strength in ohms. Default
82 - rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines
83 the DRAM side ODT strength in ohms. Default value
86 - rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines
91 - rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines
[all …]
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| /Linux-v5.10/tools/perf/pmu-events/arch/x86/sandybridge/ |
| D | memory.json | 161 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",
164 …on": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram.",
173 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",
176 …on": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram.",
185 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_MISS.DRAM",
188 …Description": "Counts all prefetch code reads that miss the LLC and the data returned from dram.",
197 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_MISS.DRAM",
200 …Description": "Counts all prefetch data reads that miss the LLC and the data returned from dram.",
209 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_MISS.DRAM",
212 …"BriefDescription": "Counts all prefetch RFOs that miss the LLC and the data returned from dram.",
[all …]
|
| /Linux-v5.10/tools/perf/pmu-events/arch/x86/nehalemex/ |
| D | memory.json | 10 "BriefDescription": "Offcore data reads satisfied by any DRAM",
32 "BriefDescription": "Offcore data reads satisfied by the local DRAM",
43 "BriefDescription": "Offcore data reads satisfied by a remote DRAM",
54 "BriefDescription": "Offcore code reads satisfied by any DRAM",
76 "BriefDescription": "Offcore code reads satisfied by the local DRAM",
87 "BriefDescription": "Offcore code reads satisfied by a remote DRAM",
98 "BriefDescription": "Offcore requests satisfied by any DRAM",
120 "BriefDescription": "Offcore requests satisfied by the local DRAM",
131 "BriefDescription": "Offcore requests satisfied by a remote DRAM",
142 "BriefDescription": "Offcore RFO requests satisfied by any DRAM",
[all …]
|
| /Linux-v5.10/tools/perf/pmu-events/arch/x86/westmereex/ |
| D | memory.json | 18 "BriefDescription": "Offcore data reads satisfied by any DRAM",
40 "BriefDescription": "Offcore data reads satisfied by the local DRAM",
51 "BriefDescription": "Offcore data reads satisfied by a remote DRAM",
62 "BriefDescription": "Offcore code reads satisfied by any DRAM",
84 "BriefDescription": "Offcore code reads satisfied by the local DRAM",
95 "BriefDescription": "Offcore code reads satisfied by a remote DRAM",
106 "BriefDescription": "Offcore requests satisfied by any DRAM",
128 "BriefDescription": "Offcore requests satisfied by the local DRAM",
139 "BriefDescription": "Offcore requests satisfied by a remote DRAM",
150 "BriefDescription": "Offcore RFO requests satisfied by any DRAM",
[all …]
|
| /Linux-v5.10/tools/perf/pmu-events/arch/x86/nehalemep/ |
| D | memory.json | 10 "BriefDescription": "Offcore data reads satisfied by any DRAM",
32 "BriefDescription": "Offcore data reads satisfied by the local DRAM",
43 "BriefDescription": "Offcore data reads satisfied by a remote DRAM",
54 "BriefDescription": "Offcore code reads satisfied by any DRAM",
76 "BriefDescription": "Offcore code reads satisfied by the local DRAM",
87 "BriefDescription": "Offcore code reads satisfied by a remote DRAM",
98 "BriefDescription": "Offcore requests satisfied by any DRAM",
120 "BriefDescription": "Offcore requests satisfied by the local DRAM",
131 "BriefDescription": "Offcore requests satisfied by a remote DRAM",
142 "BriefDescription": "Offcore RFO requests satisfied by any DRAM",
[all …]
|
| /Linux-v5.10/tools/perf/pmu-events/arch/x86/amdzen1/ |
| D | data-fabric.json | 36 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
44 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
52 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
60 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
68 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
76 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
84 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
92 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
|
| /Linux-v5.10/tools/perf/pmu-events/arch/x86/amdzen2/ |
| D | data-fabric.json | 36 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
44 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
52 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
60 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
68 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
76 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
84 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
92 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
|
| /Linux-v5.10/tools/perf/pmu-events/arch/x86/westmereep-sp/ |
| D | memory.json | 10 "BriefDescription": "Offcore data reads satisfied by any DRAM",
32 "BriefDescription": "Offcore data reads satisfied by the local DRAM",
43 "BriefDescription": "Offcore data reads satisfied by a remote DRAM",
54 "BriefDescription": "Offcore code reads satisfied by any DRAM",
76 "BriefDescription": "Offcore code reads satisfied by the local DRAM",
87 "BriefDescription": "Offcore code reads satisfied by a remote DRAM",
98 "BriefDescription": "Offcore requests satisfied by any DRAM",
120 "BriefDescription": "Offcore requests satisfied by the local DRAM",
131 "BriefDescription": "Offcore requests satisfied by a remote DRAM",
142 "BriefDescription": "Offcore RFO requests satisfied by any DRAM",
[all …]
|
| /Linux-v5.10/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | uncore-memory.json | 30 "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode",
77 "BriefDescription": "DRAM Page Activate commands sent due to a write request",
82 …DRAM Page Activate commands sent on this channel due to a write request to the iMC (Memory Control…
87 "BriefDescription": "All DRAM CAS Commands issued",
92 …DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM,…
97 "BriefDescription": "All DRAM Read CAS Commands issued (does not include underfills)",
102 …DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on D…
107 "BriefDescription": "DRAM Underfill Read CAS Commands issued",
112 …DRAM due to a partial write, on a per channel basis. CAS commands are issued to specify the addre…
117 …"BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pr…
[all …]
|
| /Linux-v5.10/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | uncore-memory.json | 30 "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode+C37",
143 "BriefDescription": "DRAM Page Activate commands sent due to a write request",
148 …DRAM Page Activate commands sent on this channel due to a write request to the iMC (Memory Control…
153 "BriefDescription": "All DRAM CAS Commands issued",
158 …DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM,…
163 "BriefDescription": "All DRAM Read CAS Commands issued (does not include underfills)",
168 …DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on D…
173 "BriefDescription": "DRAM Underfill Read CAS Commands issued",
178 …DRAM due to a partial write, on a per channel basis. CAS commands are issued to specify the addre…
183 …"BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pr…
[all …]
|
| /Linux-v5.10/drivers/tty/serial/ |
| D | icom.c | 346 void __iomem *dram_ptr = icom_port->dram; in load_code()
360 /* Zero out DRAM */ in load_code()
377 iram_ptr = (char __iomem *)icom_port->dram + ICOM_IRAM_OFFSET; in load_code()
397 iram_ptr = (char __iomem *) icom_port->dram + ICOM_IRAM_OFFSET; in load_code()
405 writeb(V2_HARDWARE, &(icom_port->dram->misc_flags)); in load_code()
411 &(icom_port->dram->HDLCConfigReg)); in load_code()
412 writeb(0x04, &(icom_port->dram->FlagFillIdleTimer)); /* 0.5 seconds */ in load_code()
413 writeb(0x00, &(icom_port->dram->CmdReg)); in load_code()
414 writeb(0x10, &(icom_port->dram->async_config3)); in load_code()
416 ICOM_ACFG_1STOP_BIT), &(icom_port->dram->async_config2)); in load_code()
[all …]
|
| /Linux-v5.10/drivers/edac/ |
| D | i3000_edac.c | 25 /* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */
31 #define I3000_EDEAP 0x70 /* Extended DRAM Error Address Pointer (8b)
36 #define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b)
68 #define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
70 * 7:0 DRAM ECC Syndrome
79 * 9 LOCK to non-DRAM Memory Flag (LCKF)
82 * 1 Multi-bit DRAM ECC Error Flag (DMERR)
83 * 0 Single-bit DRAM ECC Error Flag (DSERR)
95 * 9 SERR on LOCK to non-DRAM Memory
97 * 8 SERR on DRAM Refresh Timeout
[all …]
|
| D | i82975x_edac.c | 34 /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
35 #define I82975X_EAP 0x58 /* Dram Error Address Pointer (32b)
42 #define I82975X_DERRSYN 0x5c /* Dram Error SYNdrome (8b)
44 * 7:0 DRAM ECC Syndrome
47 #define I82975X_DES 0x5d /* Dram ERRor DeSTination (8b)
58 * 9 non-DRAM lock error (ndlock)
61 * 1 ECC UE (multibit DRAM error)
62 * 0 ECC CE (singlebit DRAM error)
76 * 9 non-DRAM lock error (ndlock)
79 * 1 ECC UE (multibit DRAM error)
[all …]
|
| D | amd64_edac.h | 56 * is within a range affected by memory hoisting. The DRAM Base
57 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
60 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
83 * The memory controller for a given node uses its DRAM CS Base and
84 * DRAM CS Mask registers to map an InputAddr to a csrow. See
169 * Function 2 - DRAM controller
317 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
339 u32 ecc_ctrl; /* DRAM ECC Control reg */
358 u32 dclr0; /* DRAM Configuration Low DCT0 reg */
359 u32 dclr1; /* DRAM Configuration Low DCT1 reg */
[all …]
|
| /Linux-v5.10/drivers/pinctrl/ |
| D | pinctrl-gemini.c | 132 "DRAM",
152 PINCTRL_PIN(2, "A3 DRAM CK"),
153 PINCTRL_PIN(3, "A4 DRAM CK N"),
154 PINCTRL_PIN(4, "A5 DRAM A5"),
155 PINCTRL_PIN(5, "A6 DRAM CKE"),
156 PINCTRL_PIN(6, "A7 DRAM DQ11"),
157 PINCTRL_PIN(7, "A8 DRAM DQ0"),
158 PINCTRL_PIN(8, "A9 DRAM DQ5"),
159 PINCTRL_PIN(9, "A10 DRAM DQ6"),
160 PINCTRL_PIN(10, "A11 DRAM DRAM VREF"),
[all …]
|
| /Linux-v5.10/drivers/usb/host/ |
| D | xhci-mvebu.c | 23 const struct mbus_dram_target_info *dram) in xhci_mvebu_mbus_config() argument
33 /* Program each DRAM CS in a seperate window */ in xhci_mvebu_mbus_config()
34 for (win = 0; win < dram->num_cs; win++) { in xhci_mvebu_mbus_config()
35 const struct mbus_dram_window *cs = dram->cs + win; in xhci_mvebu_mbus_config()
38 (dram->mbus_dram_target_id << 4) | 1, in xhci_mvebu_mbus_config()
51 const struct mbus_dram_target_info *dram; in xhci_mvebu_mbus_init_quirk() local
65 dram = mv_mbus_dram_info(); in xhci_mvebu_mbus_init_quirk()
66 xhci_mvebu_mbus_config(base, dram); in xhci_mvebu_mbus_init_quirk()
|
| /Linux-v5.10/arch/powerpc/platforms/chrp/ |
| D | gg2.h | 48 #define GG2_PCI_DRAM_BANK0 0x90 /* Control register for DRAM bank #0 */
49 #define GG2_PCI_DRAM_BANK1 0x94 /* Control register for DRAM bank #1 */
50 #define GG2_PCI_DRAM_BANK2 0x98 /* Control register for DRAM bank #2 */
51 #define GG2_PCI_DRAM_BANK3 0x9c /* Control register for DRAM bank #3 */
52 #define GG2_PCI_DRAM_BANK4 0xa0 /* Control register for DRAM bank #4 */
53 #define GG2_PCI_DRAM_BANK5 0xa4 /* Control register for DRAM bank #5 */
56 #define GG2_PCI_DRAM_CTRL 0xc0 /* DRAM control */
|
| /Linux-v5.10/drivers/net/wireless/intel/iwlwifi/ |
| D | iwl-context-info.h | 57 /* maximmum number of DRAM map entries supported by FW */
127 * struct iwl_context_info_dram - images DRAM map
128 * each entry in the map represents a DRAM chunk of up to 32 KB
129 * @umac_img: UMAC image DRAM map
130 * @lmac_img: LMAC image DRAM map
131 * @virtual_img: paged image DRAM map
164 * @core_dump_addr: core dump (debug DRAM address) start address
186 * dumping DRAM addresses
205 * @dram: firmware image addresses in DRAM
218 struct iwl_context_info_dram dram; member
[all …]
|
| D | iwl-fh.h | 87 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
88 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host
89 * from going into a power-savings mode that would cause higher DRAM latency,
95 * be sufficient to maintain fast DRAM response.
106 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident
109 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
157 * In case of DRAM read address which is not aligned to 128B, the TFH will
158 * enable transfer size which doesn't cross 64B DRAM address boundary.
166 * Tx CMD which will be updated in DRAM.
169 * In case of a DRAM Tx CMD update the TFH will update PN and Key ID
[all …]
|
| /Linux-v5.10/tools/perf/pmu-events/arch/x86/tremontx/ |
| D | uncore-other.json | 289 "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
297 …"PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes)…
302 "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
310 …"PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes)…
315 "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
323 …"PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes)…
328 "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
336 …"PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes)…
341 "BriefDescription": "Data requested of the CPU : Card writing to DRAM",
349 …"PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) t…
[all …]
|
| /Linux-v5.10/tools/perf/pmu-events/arch/x86/ivybridge/ |
| D | memory.json | 170 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",
173 …ion": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram",
182 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",
185 …ion": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram",
194 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM",
197 …ts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram",
206 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM",
209 … "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram",
218 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM",
221 … "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram",
|
| /Linux-v5.10/drivers/misc/habanalabs/include/common/ |
| D | hl_boot_if.h | 19 * CPU_BOOT_ERR0_DRAM_INIT_FAIL DRAM initialization failed.
20 * DRAM is not reliable to use.
29 * CPU_BOOT_ERR0_DRAM_SKIPPED DRAM initialization has been skipped.
30 * Skipping DRAM initialization has been
32 * and FW skipped the DRAM initialization.
33 * Host can initialize the DRAM.
86 /* Finished NICs init, reported after DRAM and NICs */
|
| /Linux-v5.10/tools/perf/pmu-events/arch/x86/knightslanding/ |
| D | memory.json | 40 …"BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Far.",
51 …riefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Local.",
84 … "BriefDescription": "Counts any Read request that accounts for data responses from DRAM Far.",
95 … "BriefDescription": "Counts any Read request that accounts for data responses from DRAM Local.",
128 …emand code reads and prefetch code read requests that accounts for data responses from DRAM Far.",
139 …and code reads and prefetch code read requests that accounts for data responses from DRAM Local.",
172 …n": "Counts Demand cacheable data write requests that accounts for data responses from DRAM Far.",
183 …: "Counts Demand cacheable data write requests that accounts for data responses from DRAM Local.",
216 …acheable data and L1 prefetch data read requests that accounts for data responses from DRAM Far.",
227 …heable data and L1 prefetch data read requests that accounts for data responses from DRAM Local.",
[all …]
|
| /Linux-v5.10/arch/arm/mach-lpc32xx/ |
| D | suspend.S | 53 @ This guarantees a small windows where DRAM isn't busy
72 @ Wait for self-refresh acknowledge, clocks to the DRAM device
84 @ Safe disable of DRAM clock in EMC block, prevents DDR sync
115 @ Re-enter run mode with self-refresh flag cleared, but no DRAM
116 @ update yet. DRAM is still in self-refresh
120 @ Restore original DRAM clock mode to restore DRAM clocks
|
