Home
last modified time | relevance | path

Searched +full:dphy +full:- +full:rx (Results 1 – 25 of 35) sorted by relevance

12

/Linux-v6.1/drivers/phy/cadence/
Dcdns-dphy-rx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
12 #include <linux/phy/phy-mipi-dphy.h>
71 struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); in cdns_dphy_rx_power_on() local
73 /* Start RX state machine. */ in cdns_dphy_rx_power_on()
77 dphy->regs + DPHY_CMN_SSM); in cdns_dphy_rx_power_on()
84 struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); in cdns_dphy_rx_power_off() local
86 writel(0, dphy->regs + DPHY_CMN_SSM); in cdns_dphy_rx_power_off()
96 /* Since CSI-2 clock is DDR, the bit rate is twice the clock rate. */ in cdns_dphy_rx_get_band_ctrl()
100 return -EOPNOTSUPP; in cdns_dphy_rx_get_band_ctrl()
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
2 obj-$(CONFIG_PHY_CADENCE_TORRENT) += phy-cadence-torrent.o
3 obj-$(CONFIG_PHY_CADENCE_DPHY) += cdns-dphy.o
4 obj-$(CONFIG_PHY_CADENCE_DPHY_RX) += cdns-dphy-rx.o
5 obj-$(CONFIG_PHY_CADENCE_SIERRA) += phy-cadence-sierra.o
6 obj-$(CONFIG_PHY_CADENCE_SALVO) += phy-cadence-salvo.o
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
16 tristate "Cadence D-PHY Support"
21 Choose this option if you have a Cadence D-PHY in your
23 cdns-dphy.
26 tristate "Cadence D-PHY Rx Support"
31 Support for Cadence D-PHY in Rx configuration.
/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dcdns,dphy-rx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/cdns,dphy-rx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence DPHY Rx
10 - Pratyush Yadav <pratyush@kernel.org>
15 - const: cdns,dphy-rx
20 "#phy-cells":
23 power-domains:
27 - compatible
[all …]
Dallwinner,sun6i-a31-mipi-dphy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 MIPI D-PHY Controller
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - const: allwinner,sun6i-a31-mipi-dphy
20 - items:
[all …]
/Linux-v6.1/drivers/phy/allwinner/
Dphy-sun6i-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2017-2018 Bootlin
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
18 #include <linux/phy/phy-mipi-dphy.h>
21 #define SUN6I_DPHY_GCTL_LANE_NUM(n) ((((n) - 1) & 3) << 4)
131 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_init() local
133 reset_control_deassert(dphy->reset); in sun6i_dphy_init()
134 clk_prepare_enable(dphy->mod_clk); in sun6i_dphy_init()
135 clk_set_rate_exclusive(dphy->mod_clk, 150000000); in sun6i_dphy_init()
142 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_configure() local
[all …]
/Linux-v6.1/drivers/phy/rockchip/
Dphy-rockchip-dphy-rx0.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Rockchip MIPI Synopsys DPHY RX0 driver
11 * chromeos-4.4 branch.
14 * Jacob Chen <jacob2.chen@rock-chips.com>
15 * Shunqian Zheng <zhengsq@rock-chips.com>
26 #include <linux/phy/phy-mipi-dphy.h>
65 "dphy-ref",
66 "dphy-cfg",
111 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
163 const struct dphy_reg *reg = &priv->drv_data->regs[index]; in rk_dphy_write_grf()
[all …]
Dphy-rockchip-inno-csidphy.c1 // SPDX-License-Identifier: GPL-2.0
3 * Rockchip MIPI RX Innosilicon DPHY driver
17 #include <linux/phy/phy-mipi-dphy.h>
60 /* Configure the count time of the THS-SETTLE by protocol. */
71 * The higher 16-bit of this register is used for write protection
93 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
145 const struct dphy_drv_data *drv_data = priv->drv_data; in write_grf_reg()
146 const struct dphy_reg *reg = &drv_data->grf_regs[index]; in write_grf_reg()
148 if (reg->offset) in write_grf_reg()
149 regmap_write(priv->grf, reg->offset, in write_grf_reg()
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/media/
Dnxp,imx8mq-mipi-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MQ MIPI CSI-2 receiver
10 - Martin Kepplinger <martin.kepplinger@puri.sm>
12 description: |-
13 This binding covers the CSI-2 RX PHY and host controller included in the
20 - fsl,imx8mq-mipi-csi2
27 - description: core is the RX Controller Core Clock input. This clock
[all …]
Dcdns,csi2rx.txt1 Cadence MIPI-CSI2 RX controller
4 The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
8 - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible
9 - reg: base address and size of the memory mapped region
10 - clocks: phandles to the clocks driving the controller
11 - clock-names: must contain:
14 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
18 - phys: phandle to the external D-PHY, phy-names must be provided
19 - phy-names: must contain "dphy", if the implementation uses an
20 external D-PHY
[all …]
/Linux-v6.1/drivers/gpu/drm/bridge/
Dtc358775.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/media-bus-format.h>
36 /* DSI D-PHY Layer Registers */
37 #define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */
38 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
39 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
40 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
41 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
42 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
43 #define COM_DPHYCONTRX 0x0038 /* DPHY Rx Common Control */
[all …]
Dcdns-dsi.c1 // SPDX-License-Identifier: GPL-2.0
27 #include <linux/phy/phy-mipi-dphy.h>
71 #define DATA_LANE_EN(x) BIT((x) - 1)
466 struct phy *dphy; member
489 return mode->hsync_start - mode->hdisplay; in mode_to_dpi_hfp()
491 return mode->crtc_hsync_start - mode->crtc_hdisplay; in mode_to_dpi_hfp()
503 dsi_timing -= dsi_pkt_overhead; in dpi_to_dsi_timing()
513 struct cdns_dsi_output *output = &dsi->output; in cdns_dsi_mode2cfg()
520 if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) in cdns_dsi_mode2cfg()
523 bpp = mipi_dsi_pixel_format_to_bpp(output->dev->format); in cdns_dsi_mode2cfg()
[all …]
Dnwl-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
15 #include <linux/media-bus-format.h>
34 #include "nwl-dsi.h"
36 #define DRV_NAME "nwl-dsi"
79 * 2. Configure DSI Host and DPHY and enable DPHY
130 int ret = dsi->error; in nwl_dsi_clear_error()
132 dsi->error = 0; in nwl_dsi_clear_error()
140 if (dsi->error) in nwl_dsi_write()
143 ret = regmap_write(dsi->regmap, reg, val); in nwl_dsi_write()
145 DRM_DEV_ERROR(dsi->dev, in nwl_dsi_write()
[all …]
/Linux-v6.1/drivers/video/fbdev/mmp/hw/
Dmmp_ctrl.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 /* ------------< LCD register >------------ */
150 #define LCD_SCLK(path) ((PATH_PN == path->id) ? LCD_CFG_SCLK_DIV :\
151 ((PATH_TV == path->id) ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV))
386 #define CFG_RXBITS(rx) (((rx) - 1)<<16) /* 0x1F~0x1 */ argument
388 #define CFG_TXBITS(tx) (((tx) - 1)<<8) /* 0x1F~0x1 */
394 #define CFG_RXBITSTO0(rx) ((rx)<<5) argument
411 1. Smart Pannel 8-bit Bus Control Register.
685 /* FIXME - JUST GUESS */
811 /* read-only */
[all …]
/Linux-v6.1/drivers/phy/amlogic/
Dphy-meson-axg-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0
3 * Meson AXG MIPI DPHY driver
48 * [0] enalbe the MIPI DPHY TxDDRClk.
97 /* [24] rx turn watch dog triggered.
98 * [23] rx esc watchdog triggered.
144 /* Watchdog for RX low power state no finished. */
188 ret = phy_init(priv->analog); in phy_meson_axg_mipi_dphy_init()
192 ret = reset_control_reset(priv->reset); in phy_meson_axg_mipi_dphy_init()
205 ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy); in phy_meson_axg_mipi_dphy_configure()
209 ret = phy_configure(priv->analog, opts); in phy_meson_axg_mipi_dphy_configure()
[all …]
/Linux-v6.1/drivers/media/platform/cadence/
Dcdns-csi2rx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Cadence MIPI-CSI2 RX Controller v1.3
18 #include <media/v4l2-ctrls.h>
19 #include <media/v4l2-device.h>
20 #include <media/v4l2-fwnode.h>
21 #include <media/v4l2-subdev.h>
71 struct phy *dphy; member
97 csi2rx->base + CSI2RX_SOFT_RESET_REG); in csi2rx_reset()
101 writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG); in csi2rx_reset()
111 ret = clk_prepare_enable(csi2rx->p_clk); in csi2rx_start()
[all …]
/Linux-v6.1/drivers/gpu/drm/kmb/
Dkmb_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2019-2020 Intel Corporation
178 clk_disable_unprepare(kmb_dsi->clk_mipi); in kmb_dsi_clk_disable()
179 clk_disable_unprepare(kmb_dsi->clk_mipi_ecfg); in kmb_dsi_clk_disable()
180 clk_disable_unprepare(kmb_dsi->clk_mipi_cfg); in kmb_dsi_clk_disable()
186 mipi_dsi_host_unregister(kmb_dsi->host); in kmb_dsi_host_unregister()
225 return -ENOMEM; in kmb_dsi_host_bridge_init()
227 dsi_host->ops = &kmb_dsi_host_ops; in kmb_dsi_host_bridge_init()
233 return -ENOMEM; in kmb_dsi_host_bridge_init()
237 dsi_host->dev = dev; in kmb_dsi_host_bridge_init()
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dsun8i-a33.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include "sun8i-a23-a33.dtsi"
46 #include <dt-bindings/thermal/thermal.h>
49 cpu0_opp_table: opp-table-cpu {
50 compatible = "operating-points-v2";
51 opp-shared;
53 opp-120000000 {
54 opp-hz = /bits/ 64 <120000000>;
[all …]
/Linux-v6.1/arch/arm64/boot/dts/rockchip/
Drk356x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
[all …]
Drk3399.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
[all …]
Dpx30.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
[all …]
/Linux-v6.1/arch/arm64/boot/dts/allwinner/
Dsun50i-a64.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun6i-rtc.h>
8 #include <dt-bindings/clock/sun8i-de2.h>
9 #include <dt-bindings/clock/sun8i-r-ccu.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/sun50i-a64-ccu.h>
12 #include <dt-bindings/reset/sun8i-de2.h>
13 #include <dt-bindings/reset/sun8i-r-ccu.h>
14 #include <dt-bindings/thermal/thermal.h>
[all …]
/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dimx8mq.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "dt-bindings/input/input.h"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interconnect/imx8mq.h>
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_hpo_dp_link_encoder.c33 enc3->base.ctx->logger
36 (enc3->regs->reg)
40 enc3->hpo_le_shift->field_name, enc3->hpo_le_mask->field_name
44 enc3->base.ctx
64 /* Reset DPHY. Only reset if going from disable to enable */ in dcn31_hpo_dp_link_enc_enable()
70 /* Configure DPHY settings */ in dcn31_hpo_dp_link_enc_enable()
82 /* Configure DPHY settings */ in dcn31_hpo_dp_link_enc_disable()
97 switch (tp_params->dp_phy_pattern) { in dcn31_hpo_dp_link_enc_set_link_test_pattern()
213 …tp_custom = (tp_params->custom_pattern[2] << 16) | (tp_params->custom_pattern[1] << 8) | tp_params… in dcn31_hpo_dp_link_enc_set_link_test_pattern()
215 …tp_custom = (tp_params->custom_pattern[5] << 16) | (tp_params->custom_pattern[4] << 8) | tp_params… in dcn31_hpo_dp_link_enc_set_link_test_pattern()
[all …]
/Linux-v6.1/drivers/gpu/drm/sprd/
Dsprd_dsi.c1 // SPDX-License-Identifier: GPL-2.0
142 return (readl(ctx->base + offset) & mask) >> shift; in dsi_reg_rd()
151 ret = readl(ctx->base + offset); in dsi_reg_wr()
154 writel(ret, ctx->base + offset); in dsi_reg_wr()
161 u32 ret = readl(ctx->base + offset); in dsi_reg_up()
163 writel((ret & ~mask) | (val & mask), ctx->base + offset); in dsi_reg_up()
169 struct dsi_context *ctx = &dsi->ctx; in regmap_tst_io_write()
172 return -EINVAL; in regmap_tst_io_write()
174 drm_dbg(dsi->drm, "reg = 0x%02x, val = 0x%02x\n", reg, val); in regmap_tst_io_write()
191 struct dsi_context *ctx = &dsi->ctx; in regmap_tst_io_read()
[all …]

12