| /Linux-v6.1/drivers/gpu/drm/i915/display/ |
| D | intel_dp_link_training.c | 41 enum drm_dp_phy dp_phy) in intel_dp_lttpr_phy_caps() argument
43 return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1]; in intel_dp_lttpr_phy_caps()
48 enum drm_dp_phy dp_phy) in intel_dp_read_lttpr_phy_caps() argument
51 u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); in intel_dp_read_lttpr_phy_caps()
53 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) { in intel_dp_read_lttpr_phy_caps()
57 drm_dp_phy_name(dp_phy)); in intel_dp_read_lttpr_phy_caps()
64 drm_dp_phy_name(dp_phy), in intel_dp_read_lttpr_phy_caps()
225 enum drm_dp_phy dp_phy) in intel_dp_lttpr_voltage_max() argument
227 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); in intel_dp_lttpr_voltage_max()
236 enum drm_dp_phy dp_phy) in intel_dp_lttpr_preemph_max() argument
[all …]
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| D | intel_dp_link_training.h | 18 enum drm_dp_phy dp_phy,
22 enum drm_dp_phy dp_phy,
26 enum drm_dp_phy dp_phy);
33 intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,
|
| /Linux-v6.1/drivers/phy/mediatek/ |
| D | phy-mtk-dp.c | 87 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_init() local
97 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE0_DRIVING_PARAM_3, in mtk_dp_phy_init()
99 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE1_DRIVING_PARAM_3, in mtk_dp_phy_init()
101 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE2_DRIVING_PARAM_3, in mtk_dp_phy_init()
103 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE3_DRIVING_PARAM_3, in mtk_dp_phy_init()
111 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_configure() local
134 regmap_write(dp_phy->regs, MTK_DP_PHY_DIG_BIT_RATE, val); in mtk_dp_phy_configure()
137 regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_PLL_CTL_1, in mtk_dp_phy_configure()
145 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_reset() local
147 regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST, in mtk_dp_phy_reset()
[all …]
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| /Linux-v6.1/include/drm/display/ |
| D | drm_dp.h | 1371 #define DP_LTTPR_BASE(dp_phy) \ argument
1373 ((dp_phy) - DP_PHY_LTTPR1))
1375 #define DP_LTTPR_REG(dp_phy, lttpr1_reg) \ argument
1376 (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg))
1379 #define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \ argument
1380 DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1)
1383 #define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \ argument
1384 DP_LTTPR_REG(dp_phy, DP_TRAINING_LANE0_SET_PHY_REPEATER1)
1390 #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \ argument
1391 DP_LTTPR_REG(dp_phy, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)
[all …]
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| D | drm_dp_helper.h | 48 enum drm_dp_phy dp_phy, bool uhbr);
50 enum drm_dp_phy dp_phy, bool uhbr);
72 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy);
485 enum drm_dp_phy dp_phy,
542 enum drm_dp_phy dp_phy,
|
| /Linux-v6.1/Documentation/devicetree/bindings/display/msm/ |
| D | dp-controller.yaml | 172 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
174 phys = <&dp_phy>;
|
| /Linux-v6.1/Documentation/devicetree/bindings/clock/ |
| D | qcom,sc7180-dispcc.yaml | 74 <&dp_phy 0>,
75 <&dp_phy 1>;
|
| D | qcom,dispcc-sm6125.yaml | 74 <&dp_phy 0>,
75 <&dp_phy 1>,
|
| D | qcom,dispcc-sm6350.yaml | 74 <&dp_phy 0>,
75 <&dp_phy 1>;
|
| D | qcom,sc7280-dispcc.yaml | 78 <&dp_phy 0>,
79 <&dp_phy 1>,
|
| D | qcom,sdm845-dispcc.yaml | 86 <&dp_phy 0>,
87 <&dp_phy 1>;
|
| D | qcom,dispcc-sm8x50.yaml | 94 <&dp_phy 0>,
95 <&dp_phy 1>;
|
| /Linux-v6.1/drivers/gpu/drm/display/ |
| D | drm_dp_helper.c | 285 enum drm_dp_phy dp_phy, bool uhbr, bool cr) in __read_delay() argument
291 if (dp_phy == DP_PHY_DPRX) { in __read_delay()
312 offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy); in __read_delay()
319 offset = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy); in __read_delay()
340 enum drm_dp_phy dp_phy, bool uhbr) in drm_dp_read_clock_recovery_delay() argument
342 return __read_delay(aux, dpcd, dp_phy, uhbr, true); in drm_dp_read_clock_recovery_delay()
347 enum drm_dp_phy dp_phy, bool uhbr) in drm_dp_read_channel_eq_delay() argument
349 return __read_delay(aux, dpcd, dp_phy, uhbr, false); in drm_dp_read_channel_eq_delay()
408 * @dp_phy: The DP PHY identifier
410 * Given the @dp_phy, get a user friendly name of the DP PHY, either "DPRX" or
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/display/bridge/ |
| D | analogix_dp.txt | 49 phys = <&dp_phy>;
|
| D | cdns,mhdp8546.yaml | 140 phys = <&dp_phy>;
|
| /Linux-v6.1/Documentation/devicetree/bindings/display/rockchip/ |
| D | analogix_dp-rockchip.txt | 52 phys = <&dp_phy>;
|
| /Linux-v6.1/Documentation/devicetree/bindings/display/exynos/ |
| D | exynos_dp.txt | 84 phys = <&dp_phy>;
|
| /Linux-v6.1/arch/arm64/boot/dts/qcom/ |
| D | sc7180.dtsi | 2707 dp_phy: dp-phy@88ea200 { label
3101 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3102 phys = <&dp_phy>;
3159 <&dp_phy 0>,
3160 <&dp_phy 1>;
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| D | sc7280.dtsi | 3350 dp_phy: dp-phy@88ea200 { label
3779 <&dp_phy 0>,
3780 <&dp_phy 1>,
4115 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
4116 phys = <&dp_phy>;
|
| D | sm6350.dtsi | 1148 dp_phy: dp-phy@88ea200 { label
|
| D | sm8250.dtsi | 2892 dp_phy: dp-phy@88ea200 { label
3707 <&dp_phy 0>,
3708 <&dp_phy 1>;
|
| /Linux-v6.1/arch/arm/boot/dts/ |
| D | exynos5250.dtsi | 813 dp_phy: video-phy-0 { label
1129 phys = <&dp_phy>;
|
| D | exynos5420.dtsi | 588 dp_phy: dp-video-phy { label
1216 phys = <&dp_phy>;
|
