| /Linux-v5.15/drivers/gpu/drm/i915/display/ |
| D | intel_dp_link_training.c | 49 static const char *intel_dp_phy_name(enum drm_dp_phy dp_phy, in intel_dp_phy_name() argument
52 if (dp_phy == DP_PHY_DPRX) in intel_dp_phy_name()
55 snprintf(buf, buf_size, "LTTPR %d", dp_phy - DP_PHY_LTTPR1 + 1); in intel_dp_phy_name()
61 enum drm_dp_phy dp_phy) in intel_dp_lttpr_phy_caps() argument
63 return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1]; in intel_dp_lttpr_phy_caps()
67 enum drm_dp_phy dp_phy) in intel_dp_read_lttpr_phy_caps() argument
69 u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); in intel_dp_read_lttpr_phy_caps()
72 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)); in intel_dp_read_lttpr_phy_caps()
74 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dp_phy, phy_caps) < 0) { in intel_dp_read_lttpr_phy_caps()
226 enum drm_dp_phy dp_phy) in intel_dp_lttpr_voltage_max() argument
[all …]
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| D | intel_dp_link_training.h | 18 enum drm_dp_phy dp_phy,
25 enum drm_dp_phy dp_phy);
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| /Linux-v5.15/Documentation/devicetree/bindings/display/msm/ |
| D | dp-controller.yaml | 118 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
120 phys = <&dp_phy>;
|
| /Linux-v5.15/Documentation/devicetree/bindings/clock/ |
| D | qcom,sc7180-dispcc.yaml | 74 <&dp_phy 0>,
75 <&dp_phy 1>;
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| D | qcom,dispcc-sm8x50.yaml | 81 <&dp_phy 0>,
82 <&dp_phy 1>;
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| D | qcom,sc7280-dispcc.yaml | 78 <&dp_phy 0>,
79 <&dp_phy 1>,
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| D | qcom,sdm845-dispcc.yaml | 86 <&dp_phy 0>,
87 <&dp_phy 1>;
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| /Linux-v5.15/include/drm/ |
| D | drm_dp_helper.h | 1342 #define DP_LTTPR_BASE(dp_phy) \ argument
1344 ((dp_phy) - DP_PHY_LTTPR1))
1346 #define DP_LTTPR_REG(dp_phy, lttpr1_reg) \ argument
1347 (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg))
1350 #define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \ argument
1351 DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1)
1354 #define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \ argument
1355 DP_LTTPR_REG(dp_phy, DP_TRAINING_LANE0_SET_PHY_REPEATER1)
1361 #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \ argument
1362 DP_LTTPR_REG(dp_phy, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)
[all …]
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| /Linux-v5.15/Documentation/devicetree/bindings/display/bridge/ |
| D | analogix_dp.txt | 49 phys = <&dp_phy>;
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| D | cdns,mhdp8546.yaml | 140 phys = <&dp_phy>;
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| /Linux-v5.15/Documentation/devicetree/bindings/display/rockchip/ |
| D | analogix_dp-rockchip.txt | 52 phys = <&dp_phy>;
|
| /Linux-v5.15/Documentation/devicetree/bindings/display/exynos/ |
| D | exynos_dp.txt | 84 phys = <&dp_phy>;
|
| /Linux-v5.15/drivers/gpu/drm/ |
| D | drm_dp_helper.c | 406 * @dp_phy: the DP PHY to get the link status for
417 enum drm_dp_phy dp_phy, in drm_dp_dpcd_read_phy_link_status() argument
422 if (dp_phy == DP_PHY_DPRX) { in drm_dp_dpcd_read_phy_link_status()
437 DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy), in drm_dp_dpcd_read_phy_link_status()
2199 * @dp_phy: LTTPR PHY to read the capabilities for
2207 enum drm_dp_phy dp_phy, in drm_dp_read_lttpr_phy_caps() argument
2213 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy), in drm_dp_read_lttpr_phy_caps()
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| /Linux-v5.15/arch/arm64/boot/dts/qcom/ |
| D | sc7180.dtsi | 2713 dp_phy: dp-phy@88ea200 { label
3106 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3107 phys = <&dp_phy>;
3164 <&dp_phy 0>,
3165 <&dp_phy 1>;
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| D | sm8250.dtsi | 2300 dp_phy: dp-phy@88ea200 { label
2855 <&dp_phy 0>,
2856 <&dp_phy 1>;
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| D | sc7280.dtsi | 1258 dp_phy: dp-phy@88ea200 { label
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| /Linux-v5.15/arch/arm/boot/dts/ |
| D | exynos5250.dtsi | 824 dp_phy: video-phy { label
1141 phys = <&dp_phy>;
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| D | exynos5420.dtsi | 598 dp_phy: dp-video-phy { label
1226 phys = <&dp_phy>;
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