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/Linux-v6.1/drivers/phy/rockchip/
Dphy-rockchip-dp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip DP PHY driver
6 * Author: Yakir Yang <ykk@@rock-chips.com>
13 #include <linux/phy/phy.h>
32 static int rockchip_set_phy_state(struct phy *phy, bool enable) in rockchip_set_phy_state() argument
34 struct rockchip_dp_phy *dp = phy_get_drvdata(phy); in rockchip_set_phy_state() local
38 ret = regmap_write(dp->grf, GRF_SOC_CON12, in rockchip_set_phy_state()
42 dev_err(dp->dev, "Can't enable PHY power %d\n", ret); in rockchip_set_phy_state()
46 ret = clk_prepare_enable(dp->phy_24m); in rockchip_set_phy_state()
48 clk_disable_unprepare(dp->phy_24m); in rockchip_set_phy_state()
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Dphy-rockchip-typec.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chris Zhong <zyw@rock-chips.com>
5 * Kever Yang <kever.yang@rock-chips.com>
7 * The ROCKCHIP Type-C PHY has two PLL clocks. The first PLL clock
8 * is used for USB3, the second PLL clock is used for DP. This Type-C PHY has
9 * 3 working modes: USB3 only mode, DP only mode, and USB3+DP mode.
11 * PHY to switch mode between USB3 and USB3+DP, without disconnecting the USB
13 * In The DP only mode, only the DP PLL needs to be powered on, and the 4 lanes
14 * are all used for DP.
24 * 2. DP only mode:
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/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dqcom,qmp-usb3-dp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QMP USB3 DP PHY controller
11 - Wesley Cheng <quic_wcheng@quicinc.com>
16 - qcom,sc7180-qmp-usb3-dp-phy
17 - qcom,sc7280-qmp-usb3-dp-phy
18 - qcom,sc8180x-qmp-usb3-dp-phy
19 - qcom,sc8280xp-qmp-usb43dp-phy
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Dtransmit-amplitude.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/transmit-amplitude.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common PHY and network PCS transmit amplitude property binding
10 Binding describing the peak-to-peak transmit amplitude for common PHYs
14 - Marek Behún <kabel@kernel.org>
17 tx-p2p-microvolt:
19 Transmit amplitude voltages in microvolts, peak-to-peak. If this property
20 contains multiple values for various PHY modes, the
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Dphy-rockchip-typec.txt1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
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Dsamsung,dp-video-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,dp-video-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC DisplayPort PHY
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
17 - samsung,exynos5250-dp-video-phy
18 - samsung,exynos5420-dp-video-phy
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Drockchip-dp-phy.txt1 Rockchip specific extensions to the Analogix Display Port PHY
2 ------------------------------------
5 - compatible : should be one of the following supported values:
6 - "rockchip.rk3288-dp-phy"
7 - clocks: from common clock binding: handle to dp clock.
9 - clock-names: from common clock binding:
11 - #phy-cells : from the generic PHY bindings, must be 0;
16 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
20 edp_phy: edp-phy {
21 compatible = "rockchip,rk3288-dp-phy";
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/Linux-v6.1/Documentation/devicetree/bindings/display/exynos/
Dexynos_dp.txt5 -dp-controller node
6 -dptx-phy node(defined inside dp-controller node)
8 For the DP-PHY initialization, we use the dptx-phy node.
9 Required properties for dptx-phy: deprecated, use phys and phy-names
10 -reg: deprecated
11 Base address of DP PHY register.
12 -samsung,enable-mask: deprecated
13 The bit-mask used to enable/disable DP PHY.
15 For the Panel initialization, we read data from dp-controller node.
16 Required properties for dp-controller:
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/Linux-v6.1/drivers/gpu/drm/xlnx/
Dzynqmp_dp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
32 #include <linux/phy/phy.h>
41 MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)");
48 MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default: 4)");
183 /* PHY configuration and status registers */
243 * struct zynqmp_dp_link_config - Common link config between source and sink
253 * struct zynqmp_dp_mode - Configured mode of DisplayPort
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/Linux-v6.1/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_link.c1 /* Copyright 2008-2013 Broadcom Corporation
8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
32 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
205 (_phy)->def_md_devad, \
211 (_phy)->def_md_devad, \
217 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
239 * bnx2x_check_lfa - This function checks if link reinitialization is required,
251 struct bnx2x *bp = params->bp; in bnx2x_check_lfa()
254 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
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/Linux-v6.1/Documentation/devicetree/bindings/display/bridge/
Danalogix_dp.txt3 Required properties for dp-controller:
4 -compatible:
6 * "samsung,exynos5-dp"
7 * "rockchip,rk3288-dp"
8 * "rockchip,rk3399-edp"
9 -reg:
12 -interrupts:
14 -clocks:
15 from common clock binding: handle to dp clock.
16 -clock-names:
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Dcdns,mhdp8546.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Swapnil Jakhade <sjakhade@cadence.com>
11 - Yuti Amonkar <yamonkar@cadence.com>
16 - cdns,mhdp8546
17 - ti,j721e-mhdp8546
22 - description:
23 Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
25 included in the associated PHY.
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/Linux-v6.1/drivers/phy/mediatek/
Dphy-mtk-dp.c1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek DisplayPort PHY driver
13 #include <linux/phy/phy.h>
85 static int mtk_dp_phy_init(struct phy *phy) in mtk_dp_phy_init() argument
87 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_init()
97 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE0_DRIVING_PARAM_3, in mtk_dp_phy_init()
99 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE1_DRIVING_PARAM_3, in mtk_dp_phy_init()
101 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE2_DRIVING_PARAM_3, in mtk_dp_phy_init()
103 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE3_DRIVING_PARAM_3, in mtk_dp_phy_init()
109 static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) in mtk_dp_phy_configure() argument
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/Linux-v6.1/drivers/gpu/drm/rockchip/
Dcdn-dp-core.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chris Zhong <zyw@rock-chips.com>
12 #include <linux/phy/phy.h>
16 #include <sound/hdmi-codec.h>
25 #include "cdn-dp-core.h"
26 #include "cdn-dp-reg.h"
62 { .compatible = "rockchip,rk3399-cdn-dp",
69 static int cdn_dp_grf_write(struct cdn_dp_device *dp, in cdn_dp_grf_write() argument
74 ret = clk_prepare_enable(dp->grf_clk); in cdn_dp_grf_write()
76 DRM_DEV_ERROR(dp->dev, "Failed to prepare_enable grf clock\n"); in cdn_dp_grf_write()
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/Linux-v6.1/drivers/gpu/drm/msm/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 ccflags-y := -I $(srctree)/$(src)
3 ccflags-y += -I $(srctree)/$(src)/disp/dpu1
4 ccflags-$(CONFIG_DRM_MSM_DSI) += -I $(srctree)/$(src)/dsi
5 ccflags-$(CONFIG_DRM_MSM_DP) += -I $(srctree)/$(src)/dp
7 msm-y := \
20 msm-$(CONFIG_DRM_MSM_HDMI) += \
33 msm-$(CONFIG_DRM_MSM_MDP4) += \
44 msm-$(CONFIG_DRM_MSM_MDP5) += \
57 msm-$(CONFIG_DRM_MSM_DPU) += \
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/Linux-v6.1/drivers/phy/samsung/
Dphy-exynos-dp-video.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung Exynos SoC series Display Port PHY driver
17 #include <linux/phy/phy.h>
20 #include <linux/soc/samsung/exynos-regs-pmu.h>
31 static int exynos_dp_video_phy_power_on(struct phy *phy) in exynos_dp_video_phy_power_on() argument
33 struct exynos_dp_video_phy *state = phy_get_drvdata(phy); in exynos_dp_video_phy_power_on()
35 /* Disable power isolation on DP-PHY */ in exynos_dp_video_phy_power_on()
36 return regmap_update_bits(state->regs, state->drvdata->phy_ctrl_offset, in exynos_dp_video_phy_power_on()
40 static int exynos_dp_video_phy_power_off(struct phy *phy) in exynos_dp_video_phy_power_off() argument
42 struct exynos_dp_video_phy *state = phy_get_drvdata(phy); in exynos_dp_video_phy_power_off()
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/Linux-v6.1/Documentation/devicetree/bindings/display/msm/
Ddp-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuogee Hsieh <quic_khsieh@quicinc.com>
19 - qcom,sc7180-dp
20 - qcom,sc7280-dp
21 - qcom,sc7280-edp
22 - qcom,sc8180x-dp
23 - qcom,sc8180x-edp
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/Linux-v6.1/drivers/gpu/drm/msm/dp/
Ddp_parser.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
10 #include <linux/phy/phy.h>
11 #include <linux/phy/phy-dp.h>
15 #define DP_LABEL "MDSS DP DISPLAY"
51 * struct dp_display_data - display related device tree data.
54 * @phy_node: reference to phy device
68 * struct dp_ctrl_resource - controller's IO related data
71 * @phy_io: phy's mapped memory address
75 struct phy *phy; member
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/Linux-v6.1/net/dsa/
Dport.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2017 Savoir-faire Linux Inc.
18 * dsa_port_notify - Notify the switching fabric of changes to a port
19 * @dp: port on which change occurred
21 * @v: event-specific value.
25 * reconfigure themselves for cross-chip operations. Can also be used to
29 static int dsa_port_notify(const struct dsa_port *dp, unsigned long e, void *v) in dsa_port_notify() argument
31 return dsa_tree_notify(dp->ds->dst, e, v); in dsa_port_notify()
34 static void dsa_port_notify_bridge_fdb_flush(const struct dsa_port *dp, u16 vid) in dsa_port_notify_bridge_fdb_flush() argument
36 struct net_device *brport_dev = dsa_port_to_bridge_port(dp); in dsa_port_notify_bridge_fdb_flush()
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/Linux-v6.1/drivers/gpu/drm/amd/display/dc/dce/
Ddce_link_encoder.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
54 SRI(DP_CONFIG, DP, id), \
55 SRI(DP_DPHY_CNTL, DP, id), \
56 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
57 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
58 SRI(DP_DPHY_SYM0, DP, id), \
59 SRI(DP_DPHY_SYM1, DP, id), \
60 SRI(DP_DPHY_SYM2, DP, id), \
61 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
62 SRI(DP_LINK_CNTL, DP, id), \
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Ddce_link_encoder.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
58 enc110->base.ctx
60 enc110->base.ctx->logger
63 (enc110->link_regs->reg)
66 (enc110->aux_regs->reg)
69 (enc110->hpd_regs->reg)
76 * ASIC-dependent, actual values for register programming
92 (reg + enc110->offsets.dig)
95 (reg + enc110->offsets.dp)
128 struct dc_bios *bp = enc110->base.ctx->dc_bios; in link_transmitter_control()
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/Linux-v6.1/drivers/phy/qualcomm/
Dphy-qcom-qmp.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #include "phy-qcom-qmp-qserdes-com.h"
10 #include "phy-qcom-qmp-qserdes-txrx.h"
12 #include "phy-qcom-qmp-qserdes-com-v3.h"
13 #include "phy-qcom-qmp-qserdes-txrx-v3.h"
15 #include "phy-qcom-qmp-qserdes-com-v4.h"
16 #include "phy-qcom-qmp-qserdes-txrx-v4.h"
17 #include "phy-qcom-qmp-qserdes-txrx-v4_20.h"
19 #include "phy-qcom-qmp-qserdes-com-v5.h"
20 #include "phy-qcom-qmp-qserdes-txrx-v5.h"
[all …]
/Linux-v6.1/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Analogix DP (Display Port) core interface driver.
18 #include <linux/phy/phy.h>
44 static int analogix_dp_init_dp(struct analogix_dp_device *dp) in analogix_dp_init_dp() argument
48 analogix_dp_reset(dp); in analogix_dp_init_dp()
50 analogix_dp_swreset(dp); in analogix_dp_init_dp()
52 analogix_dp_init_analog_param(dp); in analogix_dp_init_dp()
53 analogix_dp_init_interrupt(dp); in analogix_dp_init_dp()
56 analogix_dp_enable_sw_function(dp); in analogix_dp_init_dp()
58 analogix_dp_config_interrupt(dp); in analogix_dp_init_dp()
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/display/xlnx/
Dxlnx,zynqmp-dpsub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +-----------+ |
16 | DPDMA | --->| | --> | Video | Video +-------------+ |
17 | 4x vid | | | | | Rendering | -+--> | | | +------+
18 | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 |
19 +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+
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/Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_link_encoder.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
38 enc10->base.ctx
40 enc10->base.ctx->logger
43 (enc10->link_regs->reg)
47 enc10->link_shift->field_name, enc10->link_mask->field_name
53 * ASIC-dependent, actual values for register programming
99 struct dc_bios *bp = enc10->base.ctx->dc_bios; in link_transmitter_control()
101 result = bp->funcs->transmitter_control(bp, cntl); in link_transmitter_control()
110 /* This register resides in DP back end block; in enable_phy_bypass_mode()
121 /* This register resides in DP back end block; in disable_prbs_symbols()
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