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/Linux-v6.1/Documentation/devicetree/bindings/display/
Ddp-aux-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/dp-aux-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DisplayPort AUX bus
10 - Douglas Anderson <dianders@chromium.org>
14 are hooked up to them. This is the DP AUX bus. Over the DP AUX bus
16 particular, DP sinks support DDC over DP AUX which allows tunneling
17 a standard I2C DDC connection over the AUX channel.
19 To model this relationship, DP sinks should be placed as children
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/Linux-v6.1/drivers/gpu/drm/display/
Ddrm_dp_aux_bus.c1 // SPDX-License-Identifier: GPL-2.0
5 * The DP AUX bus is used for devices that are connected over a DisplayPort
6 * AUX bus. The device on the far side of the bus is referred to as an
9 * There is only one device connected to the DP AUX bus: an eDP panel.
10 * Though historically panels (even DP panels) have been modeled as simple
11 * platform devices, putting them under the DP AUX bus allows the panel driver
12 * to perform transactions on that bus.
27 int (*done_probing)(struct drm_dp_aux *aux);
31 * dp_aux_ep_match() - The match function for the dp_aux_bus.
41 return !!of_match_device(drv->of_match_table, dev); in dp_aux_ep_match()
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Ddrm_dp_dual_mode_helper.c35 * DOC: dp dual mode helpers
37 * Helper functions to deal with DP dual mode (aka. DP++) adaptors.
40 * Adaptor registers (if any) and the sink DDC bus may be accessed via I2C.
43 * Adaptor registers and sink DDC bus can be accessed either via I2C or
44 * I2C-over-AUX. Source devices may choose to implement either of these
51 * drm_dp_dual_mode_read - Read from the DP dual mode adaptor register(s)
52 * @adapter: I2C adapter for the DDC bus
57 * Reads @size bytes from the DP dual mode adaptor registers
69 * As sub-addressing is not supported by all adaptors, in drm_dp_dual_mode_read()
94 return -ENOMEM; in drm_dp_dual_mode_read()
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Ddrm_dp_helper.c58 struct drm_dp_aux *aux; member
64 * DOC: dp helpers
67 * levels to deal with Display Port sink devices and related things like DP aux
68 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
72 /* Helpers for DP link training */
75 return link_status[r - DP_LANE0_1_STATUS]; in dp_link_status()
149 /* DP 2.0 128b/132b */
163 /* DP 2.0 errata for 128b/132b */
183 /* DP 2.0 errata for 128b/132b */
199 /* DP 2.0 errata for 128b/132b */
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Ddrm_dp_mst_topology.c53 * DOC: dp mst helper
206 number_of_bits--; in drm_dp_msg_header_crc4()
210 bitshift--; in drm_dp_msg_header_crc4()
222 number_of_bits--; in drm_dp_msg_header_crc4()
240 number_of_bits--; in drm_dp_msg_data_crc4()
244 bitshift--; in drm_dp_msg_data_crc4()
256 number_of_bits--; in drm_dp_msg_data_crc4()
268 size += (hdr->lct / 2); in drm_dp_calc_sb_hdr_size()
279 buf[idx++] = ((hdr->lct & 0xf) << 4) | (hdr->lcr & 0xf); in drm_dp_encode_sideband_msg_hdr()
280 for (i = 0; i < (hdr->lct / 2); i++) in drm_dp_encode_sideband_msg_hdr()
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/Linux-v6.1/include/drm/display/
Ddrm_dp_aux_bus.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * The DP AUX bus is used for devices that are connected over a DisplayPort
6 * AUX bus. The devices on the far side of the bus are referred to as
17 * struct dp_aux_ep_device - Main dev structure for DP AUX endpoints
19 * This is used to instantiate devices that are connected via a DP AUX
20 * bus. Usually the device is a panel, but conceivable other devices could
26 /** @aux: Pointer to the aux bus */
27 struct drm_dp_aux *aux; member
47 int of_dp_aux_populate_bus(struct drm_dp_aux *aux,
48 int (*done_probing)(struct drm_dp_aux *aux));
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Ddrm_dp_helper.h47 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
49 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
52 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
55 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
57 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
60 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux);
75 * struct drm_dp_vsc_sdp - drm DP VSC SDP
77 * This structure represents a DP VSC SDP of drm
78 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and
79 * [Table 2-117: VSC SDP Payload for DB16 through DB18]
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Ddrm_dp_mst_helper.h52 * struct drm_dp_mst_port - MST port
56 * @mcs: message capability status - DP 1.2 spec. Protected by
58 * @ddps: DisplayPort Device Plug Status - DP 1.2. Protected by
73 * @aux: i2c aux transport to talk to device connected to this port, protected
75 * @passthrough_aux: parent aux to which DSC pass-through requests should be
76 * sent, only set if DSC pass-through is possible.
89 * only the DP MST helpers should need to touch this
130 struct drm_dp_aux aux; /* i2c bus for this port? */ member
138 * @cached_edid: for DP logical ports - make tiling work by ensuring
144 * audio-capable.
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/Linux-v6.1/Documentation/devicetree/bindings/display/msm/
Ddp-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuogee Hsieh <quic_khsieh@quicinc.com>
19 - qcom,sc7180-dp
20 - qcom,sc7280-dp
21 - qcom,sc7280-edp
22 - qcom,sc8180x-dp
23 - qcom,sc8180x-edp
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/Linux-v6.1/Documentation/devicetree/bindings/display/panel/
Dpanel-edp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-edp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Probeable (via DP AUX / EDID) eDP Panels with simple poweron sequences
10 - Douglas Anderson <dianders@chromium.org>
14 to a Embedded DisplayPort AUX bus (see display/dp-aux-bus.yaml) without
17 board, either for second-sourcing purposes or to support multiple SKUs
21 represented under the DP AUX bus. This means that we can use any
22 information provided by the DP AUX bus (including the EDID) to identify
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/Linux-v6.1/Documentation/devicetree/bindings/display/bridge/
Danalogix,anx7625.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Xin Ji <xji@analogixsemi.com>
14 The ANX7625 is an ultra-low power 4K Mobile HD Transmitter
20 - const: analogix,anx7625
29 enable-gpios:
33 reset-gpios:
37 vdd10-supply:
40 vdd18-supply:
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Dps8640.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Boichat <drinkcat@chromium.org>
13 The PS8640 is a low power MIPI-to-eDP video format converter supporting
28 powerdown-gpios:
32 reset-gpios:
36 vdd12-supply:
39 vdd33-supply:
42 aux-bus:
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Dcdns,mhdp8546.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Swapnil Jakhade <sjakhade@cadence.com>
11 - Yuti Amonkar <yamonkar@cadence.com>
16 - cdns,mhdp8546
17 - ti,j721e-mhdp8546
22 - description:
24 The AUX and PMA registers are not part of this range, they are instead
26 - description:
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Dti,sn65dsi86.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sandeep Panda <spanda@codeaurora.org>
23 enable-gpios:
27 suspend-gpios:
31 no-hpd:
37 vccio-supply:
40 vpll-supply:
43 vcca-supply:
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/Linux-v6.1/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra124-sor.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 and DP outputs.
19 pattern: "^sor@[0-9a-f]+$"
23 - enum:
24 - nvidia,tegra124-sor
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Dnvidia,tegra124-dpaux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-dpaux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra DisplayPort AUX Interface
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
18 When configured for DisplayPort AUX operation, the DPAUX controller
20 AUX channel.
24 pattern: "^dpaux@[0-9a-f]+$"
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/Linux-v6.1/drivers/gpu/drm/msm/dp/
Ddp_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
95 struct drm_dp_aux *aux; member
174 { .compatible = "qcom,sc7180-dp", .data = &sc7180_dp_cfg },
175 { .compatible = "qcom,sc7280-dp", .data = &sc7280_dp_cfg },
176 { .compatible = "qcom,sc7280-edp", .data = &sc7280_dp_cfg },
177 { .compatible = "qcom,sc8180x-dp", .data = &sc8180x_dp_cfg },
178 { .compatible = "qcom,sc8180x-edp", .data = &sc8180x_dp_cfg },
179 { .compatible = "qcom,sm8350-dp", .data = &sm8350_dp_cfg },
185 struct msm_dp *dp = dev_get_drvdata(dev); in dev_get_dp_display_private() local
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/Linux-v6.1/drivers/gpu/drm/bridge/
Dti-sn65dsi86.c1 // SPDX-License-Identifier: GPL-2.0
134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
138 * @pwm_aux: AUX-bus sub device for PWM controller functionality.
142 * @aux: Our aux channel.
153 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
154 * @comms_enabled: If true then communication over the aux channel is enabled.
159 * serves double-duty of keeping track of the direction and
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Dparade-ps8640.c1 // SPDX-License-Identifier: GPL-2.0-only
70 * page[0]: for DP control
99 struct drm_dp_aux aux; member
151 static inline struct ps8640 *aux_to_ps8640(struct drm_dp_aux *aux) in aux_to_ps8640() argument
153 return container_of(aux, struct ps8640, aux); in aux_to_ps8640()
158 struct device_node *bus, *panel; in ps8640_of_panel_on_aux_bus() local
160 bus = of_get_child_by_name(dev->of_node, "aux-bus"); in ps8640_of_panel_on_aux_bus()
161 if (!bus) in ps8640_of_panel_on_aux_bus()
164 panel = of_get_child_by_name(bus, "panel"); in ps8640_of_panel_on_aux_bus()
165 of_node_put(bus); in ps8640_of_panel_on_aux_bus()
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/Linux-v6.1/drivers/gpu/drm/bridge/analogix/
Danalogix-anx6345.c1 /* SPDX-License-Identifier: GPL-2.0-only */
32 #include "analogix-i2c-dptx.h"
33 #include "analogix-i2c-txcommon.h"
48 struct drm_dp_aux aux; member
89 static ssize_t anx6345_aux_transfer(struct drm_dp_aux *aux, in anx6345_aux_transfer() argument
92 struct anx6345 *anx6345 = container_of(aux, struct anx6345, aux); in anx6345_aux_transfer()
94 return anx_dp_aux_transfer(anx6345->map[I2C_IDX_DPTX], msg); in anx6345_aux_transfer()
103 err = anx6345_clear_bits(anx6345->map[I2C_IDX_TXCOM], in anx6345_dp_link_training()
109 err = drm_dp_dpcd_readb(&anx6345->aux, DP_MAX_LINK_RATE, &dp_bw); in anx6345_dp_link_training()
119 DRM_DEBUG_KMS("DP bandwidth (%#02x) not supported\n", dp_bw); in anx6345_dp_link_training()
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Danalogix-anx78xx.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #include "analogix-anx78xx.h"
67 struct drm_dp_aux aux; member
108 static ssize_t anx78xx_aux_transfer(struct drm_dp_aux *aux, in anx78xx_aux_transfer() argument
111 struct anx78xx *anx78xx = container_of(aux, struct anx78xx, aux); in anx78xx_aux_transfer()
112 return anx_dp_aux_transfer(anx78xx->map[I2C_IDX_TX_P0], msg); in anx78xx_aux_transfer()
119 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0], in anx78xx_set_hpd()
124 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG, in anx78xx_set_hpd()
136 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG, in anx78xx_clear_hpd()
141 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], in anx78xx_clear_hpd()
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/Linux-v6.1/drivers/gpu/drm/nouveau/dispnv50/
Ddisp.c31 #include <linux/dma-mapping.h>
69 #include <subdev/bios/dp.h>
83 chan->device = device; in nv50_chan_create()
94 &chan->user); in nv50_chan_create()
96 nvif_object_map(&chan->user, NULL, 0); in nv50_chan_create()
105 return -ENOSYS; in nv50_chan_create()
111 nvif_object_dtor(&chan->user); in nv50_chan_destroy()
121 nvif_object_dtor(&dmac->vram); in nv50_dmac_destroy()
122 nvif_object_dtor(&dmac->sync); in nv50_dmac_destroy()
124 nv50_chan_destroy(&dmac->base); in nv50_dmac_destroy()
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/Linux-v6.1/drivers/gpu/drm/gma500/
Dcdv_intel_dp.c44 * struct i2c_algo_dp_aux_data - driver interface structure for i2c over dp
45 * aux algorithm
47 * the i2c bus is quiescent
64 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; in i2c_algo_dp_aux_transaction()
67 ret = (*algo_data->aux_ch)(adapter, mode, in i2c_algo_dp_aux_transaction()
73 * I2C over AUX CH
84 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; in i2c_algo_dp_aux_address()
91 algo_data->address = address; in i2c_algo_dp_aux_address()
92 algo_data->running = true; in i2c_algo_dp_aux_address()
103 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; in i2c_algo_dp_aux_stop()
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/Linux-v6.1/drivers/gpu/drm/bridge/cadence/
Dcdns-mhdp8546-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cadence MHDP8546 DP bridge driver.
7 * Authors: Quentin Schulz <quentin.schulz@free-electrons.com>
14 * - Implement optimized mailbox communication using mailbox interrupts
15 * - Add support for power management
16 * - Add support for features like audio, MST and fast link training
17 * - Implement request_fw_cancel to handle HW_STATE
18 * - Fix asynchronous loading of firmware implementation
19 * - Add DRM helper function for cdns_mhdp_lower_link_rate
29 #include <linux/media-bus-format.h>
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/Linux-v6.1/drivers/gpu/drm/tegra/
Ddpaux.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/pinctrl/pinconf-generic.h>
25 #include "dp.h"
40 struct drm_dp_aux aux; member
66 static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux) in to_dpaux() argument
68 return container_of(aux, struct tegra_dpaux, aux); in to_dpaux()
79 u32 value = readl(dpaux->regs + (offset << 2)); in tegra_dpaux_readl()
81 trace_dpaux_readl(dpaux->dev, offset, value); in tegra_dpaux_readl()
89 trace_dpaux_writel(dpaux->dev, offset, value); in tegra_dpaux_writel()
90 writel(value, dpaux->regs + (offset << 2)); in tegra_dpaux_writel()
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