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/Linux-v5.10/Documentation/devicetree/bindings/dma/
Drenesas,usb-dmac.yaml4 $id: http://devicetree.org/schemas/dma/renesas,usb-dmac.yaml#
19 - renesas,r8a7742-usb-dmac # RZ/G1H
20 - renesas,r8a7743-usb-dmac # RZ/G1M
21 - renesas,r8a7744-usb-dmac # RZ/G1N
22 - renesas,r8a7745-usb-dmac # RZ/G1E
23 - renesas,r8a77470-usb-dmac # RZ/G1C
24 - renesas,r8a774a1-usb-dmac # RZ/G2M
25 - renesas,r8a774b1-usb-dmac # RZ/G2N
26 - renesas,r8a774c0-usb-dmac # RZ/G2E
27 - renesas,r8a774e1-usb-dmac # RZ/G2H
[all …]
Drenesas,rcar-dmac.yaml4 $id: http://devicetree.org/schemas/dma/renesas,rcar-dmac.yaml#
19 - renesas,dmac-r8a7742 # RZ/G1H
20 - renesas,dmac-r8a7743 # RZ/G1M
21 - renesas,dmac-r8a7744 # RZ/G1N
22 - renesas,dmac-r8a7745 # RZ/G1E
23 - renesas,dmac-r8a77470 # RZ/G1C
24 - renesas,dmac-r8a774a1 # RZ/G2M
25 - renesas,dmac-r8a774b1 # RZ/G2N
26 - renesas,dmac-r8a774c0 # RZ/G2E
27 - renesas,dmac-r8a774e1 # RZ/G2H
[all …]
Drenesas,shdma.txt7 DMAC instances have the same number of channels and use the same DMA
9 multiplexer node. Even if there is only one such DMAC instance on a system, it
27 "renesas,shdma-r8a73a4" for the system DMAC on r8a73a4 SoC
30 dmac: dma-multiplexer@0 {
82 dmas = <&dmac 0xd1
83 &dmac 0xd2>;
Dsirfsoc-dma.txt6 - compatible: Should be "sirf,prima2-dmac", "sirf,atlas7-dmac" or
7 "sirf,atlas7-dmac-v2"
18 compatible = "sirf,prima2-dmac";
Dsnps,dw-axi-dmac.txt5 - reg: Address range of the DMAC registers. This should include
7 - interrupt: Should contain the DMAC interrupt number.
21 supported by DMAC is used. [1:256]
25 dmac: dma-controller@80000 {
Dsocionext,uniphier-mio-dmac.yaml4 $id: http://devicetree.org/schemas/dma/socionext,uniphier-mio-dmac.yaml#
21 const: socionext,uniphier-mio-dmac
55 dmac: dma-controller@5a000000 {
56 compatible = "socionext,uniphier-mio-dmac";
Dadi,axi-dmac.txt1 Analog Devices AXI-DMAC DMA controller
4 - compatible: Must be "adi,axi-dmac-1.00.a".
36 DMA clients connected to the AXI-DMAC DMA controller must use the format
43 compatible = "adi,axi-dmac-1.00.a";
/Linux-v5.10/drivers/dma/
Ddma-axi-dmac.c3 * Driver for the Analog Devices AXI-DMAC core
26 #include <dt-bindings/dma/axi-dmac.h>
32 * The AXI-DMAC is a soft IP core that is used in FPGA designs. The core has
205 struct axi_dmac *dmac = chan_to_axi_dmac(chan); in axi_dmac_start_transfer() local
212 val = axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER); in axi_dmac_start_transfer()
245 sg->id = axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_ID); in axi_dmac_start_transfer()
248 axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, sg->dest_addr); in axi_dmac_start_transfer()
249 axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, sg->dest_stride); in axi_dmac_start_transfer()
253 axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, sg->src_addr); in axi_dmac_start_transfer()
254 axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, sg->src_stride); in axi_dmac_start_transfer()
[all …]
Dpl330.c318 * One cycle of DMAC operation.
370 /* A DMAC Thread */
376 /* Parent DMAC */
377 struct pl330_dmac *dmac; member
393 /* In the DMAC pool */
427 /* Pointer to the DMAC that manages this channel,
429 * As the parent, this DMAC also provides descriptors
432 struct pl330_dmac *dmac; member
438 * Hardware channel thread of PL330 DMAC. NULL if the channel is
463 /* Pool of descriptors available for the DMAC's channels */
[all …]
/Linux-v5.10/drivers/dma/sh/
Dusb-dmac.c7 * based on rcar-dmac.c
46 * @residue: residue after the DMAC completed a transfer
48 * @done_cookie: cookie after the DMAC completed a transfer
74 * @desc_freed: freed descriptors after the DMAC completed a transfer
95 * @channels: array of DMAC channels
151 static void usb_dmac_write(struct usb_dmac *dmac, u32 reg, u32 data) in usb_dmac_write() argument
153 writel(data, dmac->iomem + reg); in usb_dmac_write()
156 static u32 usb_dmac_read(struct usb_dmac *dmac, u32 reg) in usb_dmac_read() argument
158 return readl(dmac->iomem + reg); in usb_dmac_read()
244 static int usb_dmac_init(struct usb_dmac *dmac) in usb_dmac_init() argument
[all …]
Drcar-dmac.c194 * @channels: array of DMAC channels
214 * @chan_offset_base: DMAC channels base offset
215 * @chan_offset_stride: DMAC channels offset stride
303 static void rcar_dmac_write(struct rcar_dmac *dmac, u32 reg, u32 data) in rcar_dmac_write() argument
306 writew(data, dmac->iomem + reg); in rcar_dmac_write()
308 writel(data, dmac->iomem + reg); in rcar_dmac_write()
311 static u32 rcar_dmac_read(struct rcar_dmac *dmac, u32 reg) in rcar_dmac_read() argument
314 return readw(dmac->iomem + reg); in rcar_dmac_read()
316 return readl(dmac->iomem + reg); in rcar_dmac_read()
383 * first descriptor at beginning of transfer by the DMAC like it in rcar_dmac_chan_start_xfer()
[all …]
/Linux-v5.10/sound/soc/sh/rcar/
Ddma.c3 // Renesas R-Car Audio DMAC support
13 * Audio DMAC peri peri register
66 * Audio DMAC
173 * in case of monaural data writing or reading through Audio-DMAC in rsnd_dmaen_start()
263 struct rsnd_dma_ctrl *dmac = rsnd_priv_to_dmac(priv); in rsnd_dmaen_attach() local
291 dmac->dmaen_num++; in rsnd_dmaen_attach()
328 * Audio DMAC peri peri
417 #define rsnd_dmapp_addr(dmac, dma, reg) \ argument
418 (dmac->base + 0x20 + reg + \
424 struct rsnd_dma_ctrl *dmac = rsnd_priv_to_dmac(priv); in rsnd_dmapp_write() local
[all …]
/Linux-v5.10/tools/testing/selftests/drivers/net/mlxsw/
Ddevlink_trap_l2_drops.sh119 local dmac=de:ad:be:ef:13:37
128 flower dst_mac $dmac action drop
130 $MZ $h1 "$opt" -c 0 -p 100 -a own -b $dmac -t ip -d 1msec -q &
179 local dmac=de:ad:be:ef:13:37
188 flower dst_mac $dmac action drop
190 $MZ $h1 -Q $vid -c 0 -p 100 -a own -b $dmac -t ip -d 1msec -q &
221 local dmac=de:ad:be:ef:13:37
231 flower dst_mac $dmac action drop
233 $MZ $h1 -Q $vid -c 0 -p 100 -a own -b $dmac -t ip -d 1msec -q &
290 local dmac=de:ad:be:ef:13:37
[all …]
/Linux-v5.10/arch/sh/kernel/cpu/sh4/
Dsetup-sh7750.c182 HUDI, GPIOI, DMAC, enumerator
208 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
224 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
225 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
226 INTC_VECT(DMAC, 0x6c0),
237 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
238 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
239 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
240 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
241 INTC_VECT(DMAC, 0x6c0),
Dsetup-sh7760.c21 HUDI, GPIOI, DMAC, enumerator
45 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
46 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
47 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
48 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
49 INTC_VECT(DMAC, 0x6c0),
106 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } },
/Linux-v5.10/drivers/rapidio/devices/
Dtsi721_dma.c75 tsi_debug(DMA, &bdma_chan->dchan.dev->device, "DMAC%d", bdma_chan->id); in tsi721_bdma_ch_init()
92 "DMAC%d descriptors @ %p (phys = %pad)", in tsi721_bdma_ch_init()
116 "DMAC%d desc status FIFO @ %p (phys = %pad) size=0x%x", in tsi721_bdma_ch_init()
157 "Unable to get MSI-X for DMAC%d-DONE", in tsi721_bdma_ch_init()
169 "Unable to get MSI-X for DMAC%d-INT", in tsi721_bdma_ch_init()
307 "DMAC%d Attempt to start non-idle channel", in tsi721_start_dma()
314 "DMAC%d Attempt to start DMA with no BDs ready %d", in tsi721_start_dma()
319 tsi_debug(DMA, &bdma_chan->dchan.dev->device, "DMAC%d (wrc=%d) %d", in tsi721_start_dma()
426 tsi_err(ch_dev, "DMAC%d ERR: Attempt to use non-idle channel", in tsi721_submit_sg()
450 tsi_debug(DMA, ch_dev, "DMAC%d BD ring status: rdi=%d wri=%d", in tsi721_submit_sg()
[all …]
/Linux-v5.10/drivers/dma/dw-axi-dmac/
Ddw-axi-dmac.h121 #define DMAC_ID 0x000 /* R DMAC ID */
122 #define DMAC_COMPVER 0x008 /* R DMAC Component Version */
123 #define DMAC_CFG 0x010 /* R/W DMAC Configuration */
124 #define DMAC_CHEN 0x018 /* R/W DMAC Channel Enable */
125 #define DMAC_CHEN_L 0x018 /* R/W DMAC Channel Enable 00-31 */
126 #define DMAC_CHEN_H 0x01C /* R/W DMAC Channel Enable 32-63 */
127 #define DMAC_INTSTATUS 0x030 /* R DMAC Interrupt Status */
128 #define DMAC_COMMON_INTCLEAR 0x038 /* W DMAC Interrupt Clear */
129 #define DMAC_COMMON_INTSTATUS_ENA 0x040 /* R DMAC Interrupt Status Enable */
130 #define DMAC_COMMON_INTSIGNAL_ENA 0x048 /* R/W DMAC Interrupt Signal Enable */
[all …]
/Linux-v5.10/drivers/mmc/host/
Drenesas_sdhi_internal_dmac.c3 * DMA support for Internal DMAC with SDHI SD/SDIO controller
62 * - Since this SDHI DMAC register set has 16 but 32-bit width, we
68 * Workaround for avoiding to use RX DMAC by multiple channels.
70 * RX DMAC simultaneously, sometimes hundreds of bytes data are not
71 * stored into the system memory even if the DMAC interrupt happened.
72 * So, this driver then uses one RX DMAC channel only.
99 /* DMAC can handle 32bit blk count but only 1 segment */
114 /* DMAC can handle 32bit blk count but only 1 segment */
189 /* This DMAC cannot handle if buffer is not 8-bytes alignment */ in renesas_sdhi_internal_dmac_start_dma()
227 /* start the DMAC */ in renesas_sdhi_internal_dmac_issue_tasklet_fn()
[all …]
/Linux-v5.10/arch/sh/include/asm/
Ddma.h18 * channel configuration. Consult your DMAC documentation and module
28 * DMAC (dma_info) flags
42 * Transfer end interrupt, inherited from DMAC.
63 char dev_id[16]; /* unique name per DMAC of channel */
65 unsigned int chan; /* DMAC channel number */
121 extern int request_dma_bycap(const char **dmac, const char **caps,
134 extern int register_chan_caps(const char *dmac, struct dma_chan_caps *capslist);
/Linux-v5.10/include/linux/
Dsh_dma.h34 * struct sh_dmae_channel - DMAC channel platform data
50 * struct sh_dmae_pdata - DMAC platform data
66 * @no_dmars: DMAC has no DMARS registers
67 * @chclr_present: DMAC has one or several CHCLR registers
69 * @slave_only: DMAC cannot be used for MEMCPY
99 /* Definitions for the SuperH DMAC */
/Linux-v5.10/drivers/gpu/drm/nouveau/dispnv50/
Ddisp.c118 nv50_dmac_destroy(struct nv50_dmac *dmac) in nv50_dmac_destroy() argument
120 nvif_object_dtor(&dmac->vram); in nv50_dmac_destroy()
121 nvif_object_dtor(&dmac->sync); in nv50_dmac_destroy()
123 nv50_chan_destroy(&dmac->base); in nv50_dmac_destroy()
125 nvif_mem_dtor(&dmac->_push.mem); in nv50_dmac_destroy()
131 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push); in nv50_dmac_kick() local
133 dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr; in nv50_dmac_kick()
134 if (dmac->put != dmac->cur) { in nv50_dmac_kick()
138 if (dmac->push->mem.type & NVIF_MEM_VRAM) { in nv50_dmac_kick()
139 struct nvif_device *device = dmac->base.device; in nv50_dmac_kick()
[all …]
/Linux-v5.10/arch/sh/drivers/dma/
DKconfig6 bool "SuperH on-chip DMA controller (DMAC) support"
40 DMAC supports. This will be 4 for SH7750/SH7751/Sh7750S/SH7091 and 8 for the
52 tristate "PowerVR 2 DMAC support"
56 As this chains off of the on-chip DMAC, that must also be
Ddmabrg.c20 * from the traditional SH DMAC (although it blocks usage of DMAC 0)
162 /* request DMAC channel 0 before anyone else can get it */ in dmabrg_init()
163 ret = request_dma(0, "DMAC 0 (DMABRG)"); in dmabrg_init()
165 printk(KERN_INFO "DMABRG: DMAC ch0 not reserved!\n"); in dmabrg_init()
170 __raw_writel(0x94000000, DMARSRA); /* enable DMABRG in DMAC 0 */ in dmabrg_init()
172 /* enable DMABRG mode, enable the DMAC */ in dmabrg_init()
/Linux-v5.10/arch/sh/kernel/cpu/sh3/
Dsetup-sh7705.c26 DMAC, SCIF0, SCIF2, ADC_ADI, USB, enumerator
37 INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
38 INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
60 { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, SCIF0, SCIF2, ADC_ADI } },
/Linux-v5.10/drivers/net/ethernet/renesas/
Dsh_eth.h28 /* E-DMAC registers */
495 unsigned hw_swap:1; /* E-DMAC has DE bit in EDMR */
496 unsigned nbst:1; /* E-DMAC has NBST bit in EDMR */
497 unsigned rpadir:1; /* E-DMAC has RPADIR */
498 unsigned no_trimd:1; /* E-DMAC DOES NOT have TRIMD */
499 unsigned no_ade:1; /* E-DMAC DOES NOT have ADE bit in EESR */
500 unsigned no_xdfar:1; /* E-DMAC DOES NOT have RDFAR/TDFAR */
501 unsigned xdfar_rw:1; /* E-DMAC has writeable RDFAR/TDFAR */
502 unsigned csmr:1; /* E-DMAC has CSMR */
510 unsigned dual_port:1; /* Dual EtherC/E-DMAC */

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