| /Linux-v5.10/sound/pci/ |
| D | ad1889.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2004, Kyle McMartin <kyle@parisc-linux.org>
9 #define AD_DS_WSMC 0x00 /* wave/synthesis channel mixer control */
10 #define AD_DS_WSMC_SYEN 0x0004 /* synthesis channel enable */
12 #define AD_DS_WSMC_WA16 0x0100 /* wave channel 16bit select */
13 #define AD_DS_WSMC_WAST 0x0200 /* wave channel stereo select */
14 #define AD_DS_WSMC_WAEN 0x0400 /* wave channel enable */
17 #define AD_DS_RAMC 0x02 /* resampler/ADC channel mixer control */
18 #define AD_DS_RAMC_AD16 0x0001 /* ADC channel 16bit select */
19 #define AD_DS_RAMC_ADST 0x0002 /* ADC channel stereo select */
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| /Linux-v5.10/arch/parisc/include/asm/ |
| D | dma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* asm/dma.h: Defines for using and allocating dma channels.
4 * High DMA channel support & info by Hannu Savolainen
18 ** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up
26 /* The maximum address that we can perform a DMA transfer to on this platform
27 ** New dynamic DMA interfaces should obsolete this....
32 ** We don't have DMA channels... well V-class does but the
33 ** Dynamic DMA Mapping interface will support them... right? :^)
34 ** Note: this is not relevant right now for PA-RISC, but we cannot
36 ** won't compile :-(
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| /Linux-v5.10/arch/mips/include/asm/mach-bcm63xx/ |
| D | bcm63xx_dev_enet.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
44 /* DMA channel enable mask */
47 /* DMA channel interrupt mask */
50 /* DMA engine has internal SRAM */
53 /* DMA channel register width */
56 /* DMA descriptor shift */
59 /* dma channel ids */
89 /* DMA channel enable mask */
92 /* DMA channel interrupt mask */
95 /* DMA channel register width */
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| /Linux-v5.10/include/linux/ |
| D | dmaengine.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
18 * typedef dma_cookie_t - an opaque DMA cookie
20 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
31 * enum dma_status - DMA transaction status
46 * enum dma_transaction_type - DMA transaction types/indexes
49 * automatically set as dma devices are registered.
68 /* last transaction type for creation of the capabilities mask */
73 * enum dma_transfer_direction - dma transfer mode and direction indicator
89 * ----------------------------
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| D | sh_dma.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
12 #include <linux/shdma-base.h>
17 /* Used by slave DMA clients to request DMA to/from a specific peripheral */
23 * Supplied by platforms to specify, how a DMA channel has to be configured for
34 * struct sh_dmae_channel - DMAC channel platform data
36 * @dmars: channel DMARS register offset
37 * @chclr_offset: channel CHCLR register offset
38 * @dmars_bit: channel DMARS field offset within the register
39 * @chclr_bit: bit position, to be set to reset the channel
50 * struct sh_dmae_pdata - DMAC platform data
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| /Linux-v5.10/Documentation/devicetree/bindings/dma/ |
| D | brcm,bcm2835-dma.txt | 1 * BCM2835 DMA controller
3 The BCM2835 DMA controller has 16 channels in total.
11 - compatible: Should be "brcm,bcm2835-dma".
12 - reg: Should contain DMA registers location and length.
13 - interrupts: Should contain the DMA interrupts associated
14 to the DMA channels in ascending order.
15 - interrupt-names: Should contain the names of the interrupt
17 Use "dma-shared-all" for the common interrupt line
18 that is shared by all dma channels.
19 - #dma-cells: Must be <1>, the cell in the dmas property of the
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| D | ti-edma.txt | 3 The eDMA3 consists of two components: Channel controller (CC) and Transfer
4 Controller(s) (TC). The CC is the main entry for DMA users since it is
5 responsible for the DMA channel handling, while the TCs are responsible to
6 execute the actual DMA tansfer.
8 ------------------------------------------------------------------------------
9 eDMA3 Channel Controller
12 --------------------
13 - compatible: Should be:
14 - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
16 - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
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| /Linux-v5.10/arch/arm/mach-pxa/include/mach/ |
| D | regs-lcd.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
22 #define FBR0 (0x020) /* DMA Channel 0 Frame Branch Register */
23 #define FBR1 (0x024) /* DMA Channel 1 Frame Branch Register */
24 #define FBR2 (0x028) /* DMA Channel 2 Frame Branch Register */
25 #define FBR3 (0x02C) /* DMA Channel 2 Frame Branch Register */
26 #define FBR4 (0x030) /* DMA Channel 2 Frame Branch Register */
27 #define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */
28 #define FBR6 (0x114) /* DMA Channel 2 Frame Branch Register */
51 #define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */
52 #define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */
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| /Linux-v5.10/Documentation/driver-api/rapidio/ |
| D | tsi721.rst | 2 RapidIO subsystem mport driver for IDT Tsi721 PCI Express-to-SRIO bridge.
10 doorbells, inbound maintenance port-writes and RapidIO messaging.
12 To generate SRIO maintenance transactions this driver uses one of Tsi721 DMA
23 - 'dbg_level'
24 - This parameter allows to control amount of debug information
28 For mask definitions see 'drivers/rapidio/devices/tsi721.h'
32 - 'dma_desc_per_channel'
33 - This parameter defines number of hardware buffer
34 descriptors allocated for each registered Tsi721 DMA channel.
37 - 'dma_txqueue_sz'
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| /Linux-v5.10/arch/mips/include/asm/ |
| D | dma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
5 * High DMA channel support & info by Hannu Savolainen
9 * and can only be used for expansion cards. Onboard DMA controllers, such
30 * NOTES about DMA transfers:
32 * controller 1: channels 0-3, byte operations, ports 00-1F
33 * controller 2: channels 4-7, word operations, ports C0-DF
35 * - ALL registers are 8 bits only, regardless of transfer size
36 * - channel 4 is not used - cascades 1 into 2.
37 * - channels 0-3 are byte - addresses/counts are for physical bytes
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| /Linux-v5.10/sound/core/ |
| D | pcm_dmaengine.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Lars-Peter Clausen <lars@metafoo.de>
7 * imx-pcm-dma-mx2.c, Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
8 * mxs-pcm.c, Copyright (C) 2011 Freescale Semiconductor, Inc.
9 * ep93xx-pcm.c, Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
32 return substream->runtime->private_data; in substream_to_prtd()
39 return prtd->dma_chan; in snd_dmaengine_pcm_get_chan()
44 * snd_hwparams_to_dma_slave_config - Convert hw_params to dma_slave_config
47 * @slave_config: DMA slave config
61 return -EINVAL; in snd_hwparams_to_dma_slave_config()
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| /Linux-v5.10/arch/x86/include/asm/ |
| D | dma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
5 * High DMA channel support & info by Hannu Savolainen
24 * NOTES about DMA transfers:
26 * controller 1: channels 0-3, byte operations, ports 00-1F
27 * controller 2: channels 4-7, word operations, ports C0-DF
29 * - ALL registers are 8 bits only, regardless of transfer size
30 * - channel 4 is not used - cascades 1 into 2.
31 * - channels 0-3 are byte - addresses/counts are for physical bytes
32 * - channels 5-7 are word - addresses/counts are for physical words
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| /Linux-v5.10/drivers/dma/ |
| D | at_xdmac.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for the Atmel Extensible DMA Controller (aka XDMAC on AT91 systems)
11 #include <dt-bindings/dma/at91.h>
36 #define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */
38 #define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */
39 #define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */
40 #define AT_XDMAC_GS 0x24 /* Global Channel Status Register */
41 #define AT_XDMAC_GRS 0x28 /* Global Channel Read Suspend Register */
43 #define AT_XDMAC_GRWS 0x30 /* Global Channel Read Write Suspend Register */
44 #define AT_XDMAC_GRWR 0x34 /* Global Channel Read Write Resume Register */
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| D | dmaengine.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
7 * This code implements the DMA subsystem. It provides a HW-neutral interface
9 * if present, and allows different HW DMA drivers to register as providing
21 * A subsystem can get access to a channel by calling dmaengine_get() followed
22 * by dma_find_channel(), or if it has need for an exclusive channel it can call
23 * dma_request_channel(). Once a channel is allocated a reference is taken
29 * See Documentation/driver-api/dmaengine for more details
35 #include <linux/dma-mapping.h>
63 /* --- debugfs implementation --- */
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| /Linux-v5.10/arch/alpha/include/asm/ |
| D | dma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * include/asm-alpha/dma.h
5 * This is essentially the same as the i386 DMA stuff, as the AlphaPCs
6 * use ISA-compatible dma. The only extension is support for high-page
7 * registers that allow to set the top 8 bits of a 32-bit DMA address.
8 * This register should be written last when setting up a DMA address
9 * as this will also enable DMA across 64 KB boundaries.
12 /* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
13 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
15 * High DMA channel support & info by Hannu Savolainen
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| /Linux-v5.10/arch/powerpc/include/asm/ |
| D | dma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 * Defines for using and allocating dma channels.
9 * High DMA channel support & info by Hannu Savolainen
19 * basically just enough here to get kernel/dma.c to compile.
29 /* The maximum address that we can perform a DMA transfer to on this platform */
42 * NOTES about DMA transfers:
44 * controller 1: channels 0-3, byte operations, ports 00-1F
45 * controller 2: channels 4-7, word operations, ports C0-DF
47 * - ALL registers are 8 bits only, regardless of transfer size
48 * - channel 4 is not used - cascades 1 into 2.
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| /Linux-v5.10/sound/soc/fsl/ |
| D | fsl_asrc_dma.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Freescale ASRC ALSA SoC Platform (DMA) driver
9 #include <linux/dma-mapping.h>
11 #include <linux/platform_data/dma-imx.h>
37 chan->private = param; in filter()
45 struct snd_pcm_runtime *runtime = substream->runtime; in fsl_asrc_dma_complete()
46 struct fsl_asrc_pair *pair = runtime->private_data; in fsl_asrc_dma_complete()
48 pair->pos += snd_pcm_lib_period_bytes(substream); in fsl_asrc_dma_complete()
49 if (pair->pos >= snd_pcm_lib_buffer_bytes(substream)) in fsl_asrc_dma_complete()
50 pair->pos = 0; in fsl_asrc_dma_complete()
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| /Linux-v5.10/arch/powerpc/boot/dts/fsl/ |
| D | mpc8641si-post.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
9 #address-cells = <2>;
10 #size-cells = <1>;
11 compatible = "fsl,mpc8641-localbus", "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
19 compatible = "fsl,mpc8641-soc", "simple-bus";
20 bus-frequency = <0>;
22 mcm-law@0 {
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| /Linux-v5.10/drivers/usb/musb/ |
| D | ux500_dma.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * U8500 DMA support code
8 * Copyright (C) 2011 ST-Ericsson SA
18 #include <linux/dma-mapping.h>
22 #include <linux/platform_data/usb-musb-ux500.h>
31 struct dma_channel channel; member
50 /* Work function invoked from DMA callback to handle rx transfers. */
53 struct dma_channel *channel = private_data; in ux500_dma_callback() local
54 struct ux500_dma_channel *ux500_channel = channel->private_data; in ux500_dma_callback()
55 struct musb_hw_ep *hw_ep = ux500_channel->hw_ep; in ux500_dma_callback()
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| /Linux-v5.10/arch/powerpc/boot/dts/ |
| D | mpc8349emitxgp.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MPC8349E-mITX-GP Device Tree Source
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <32768>;
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| D | sbc8548-post.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #address-cells = <1>;
13 #size-cells = <1>;
16 bus-frequency = <0>;
17 compatible = "simple-bus";
19 ecm-law@0 {
20 compatible = "fsl,ecm-law";
22 fsl,num-laws = <10>;
26 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
29 interrupt-parent = <&mpic>;
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| D | asp834x-redboot.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
12 compatible = "analogue-and-micro,asp8347e";
13 #address-cells = <1>;
14 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <32768>;
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| /Linux-v5.10/drivers/spi/ |
| D | spi-dw-dma.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Special handling for DW DMA core
9 #include <linux/dma-mapping.h>
14 #include <linux/platform_data/dma-dw.h>
18 #include "spi-dw.h"
29 if (s->dma_dev != chan->device->dev) in dw_spi_dma_chan_filter()
32 chan->private = s; in dw_spi_dma_chan_filter()
42 def_burst = dws->fifo_len / 2; in dw_spi_dma_maxburst_init()
44 ret = dma_get_slave_caps(dws->rxchan, &caps); in dw_spi_dma_maxburst_init()
50 dws->rxburst = min(max_burst, def_burst); in dw_spi_dma_maxburst_init()
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| /Linux-v5.10/drivers/dma/dw/ |
| D | core.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Core driver for the Synopsys DesignWare DMA Controller
5 * Copyright (C) 2007-2008 Atmel Corporation
6 * Copyright (C) 2010-2011 ST Microelectronics
13 #include <linux/dma-mapping.h>
28 * This supports the Synopsys "DesignWare AHB Central DMA Controller",
37 /* The set of bus widths supported by the DMA controller */
44 /*----------------------------------------------------------------------*/
48 return &chan->dev->device; in chan2dev()
53 return to_dw_desc(dwc->active_list.next); in dwc_first_active()
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| /Linux-v5.10/drivers/iio/adc/ |
| D | at91-sama5d2_adc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/dma-mapping.h>
84 /* Channel Sequence Register 1 */
86 /* Channel Sequence Register 2 */
88 /* Channel Enable Register */
90 /* Channel Disable Register */
92 /* Channel Status Register */
98 /* Interrupt Enable Register - TS X measurement ready */
100 /* Interrupt Enable Register - TS Y measurement ready */
102 /* Interrupt Enable Register - TS pressure measurement ready */
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