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/Linux-v5.10/Documentation/devicetree/bindings/clock/
Dqcom,sc7180-dispcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc7180-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller Binding for SC7180
10 - Taniya Das <tdas@codeaurora.org>
14 power domains on SC7180.
16 See also dt-bindings/clock/qcom,dispcc-sc7180.h.
20 const: qcom,sc7180-dispcc
24 - description: Board XO source
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/Linux-v5.10/drivers/clk/qcom/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
4 clk-qcom-y += common.o
5 clk-qcom-y += clk-regmap.o
6 clk-qcom-y += clk-alpha-pll.o
7 clk-qcom-y += clk-pll.o
8 clk-qcom-y += clk-rcg.o
9 clk-qcom-y += clk-rcg2.o
10 clk-qcom-y += clk-branch.o
11 clk-qcom-y += clk-regmap-divider.o
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Ddispcc-sc7180.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
13 #include "clk-alpha-pll.h"
14 #include "clk-branch.h"
15 #include "clk-rcg.h"
16 #include "clk-regmap-divider.h"
693 { .compatible = "qcom,sc7180-dispcc" },
721 .name = "sc7180-dispcc",
738 MODULE_DESCRIPTION("QTI DISP_CC SC7180 Driver");
/Linux-v5.10/arch/arm64/boot/dts/qcom/
Dsc7180.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * SC7180 SoC device tree source
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
15 #include <dt-bindings/interconnect/qcom,sc7180.h>
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/Linux-v5.10/drivers/phy/qualcomm/
Dphy-qcom-qmp.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
23 #include <dt-bindings/phy/phy.h>
25 #include "phy-qcom-qmp.h"
83 * if yes, then offset gives index in the reg-layout
115 /* set of registers with offsets different per-PHY */
1827 /* struct qmp_phy_cfg - per-PHY initialization config */
1829 /* phy-type - PCIE/UFS/USB */
1834 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1898 * struct qmp_phy - per-lane phy descriptor
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