Searched +full:desired +full:- +full:num +full:- +full:phases (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#13 controller that are not already included in the synopsys-dw-mshc-common.yaml17 - $ref: "synopsys-dw-mshc-common.yaml#"20 - Heiko Stuebner <heiko@sntech.de>27 - const: rockchip,rk2928-dw-mshc29 - const: rockchip,rk3288-dw-mshc30 - items:[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later11 #include <linux/mmc/slot-gpio.h>16 #include "dw_mmc-pltfm.h"31 struct dw_mci_rockchip_priv_data *priv = host->priv; in dw_mci_rk3288_set_ios()36 if (ios->clock == 0) in dw_mci_rk3288_set_ios()43 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div)) in dw_mci_rk3288_set_ios()46 * DDR52 8-bit mode. in dw_mci_rk3288_set_ios()48 if (ios->bus_width == MMC_BUS_WIDTH_8 && in dw_mci_rk3288_set_ios()49 ios->timing == MMC_TIMING_MMC_DDR52) in dw_mci_rk3288_set_ios()50 cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV; in dw_mci_rk3288_set_ios()[all …]
1 /* SPDX-License-Identifier: GPL-2.0-only */4 * Copyright 2009-2018 Solarflare Communications Inc.5 * Copyright 2019-2020 Xilinx Inc.13 /* Power-on reset state */35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */38 /* The rest of these are firmware-defined */46 /* Values to be written to the per-port status dword in shared71 * | | \--- Response72 * | \------- Error73 * \------------------------------ Resync (always set)[all …]
