define (full) in projects: Linux-v5.10 - OpenGrok search results

Project(s)

Full Search
Definition
Symbol
File Path
History
Type

Searched full:define (Results 1 – 25 of 2088) sorted by relevance

12 3 4 5 6 7 8 9 10 >>...84

/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/dce/
D	dce_12_0_offset.h	22 #define _dce_12_0_OFFSET_HEADER 28 #define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR … 29 #define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_BASE_IDX … 34 #define mmdispdec_VGA_MEM_READ_PAGE_ADDR … 35 #define mmdispdec_VGA_MEM_READ_PAGE_ADDR_BASE_IDX … 40 #define mmDC_PERFMON0_PERFCOUNTER_CNTL … 41 #define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX … 42 #define mmDC_PERFMON0_PERFCOUNTER_CNTL2 … 43 #define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX … 44 #define mmDC_PERFMON0_PERFCOUNTER_STATE … [all …]
D	dce_11_0_sh_mask.h	25 #define DCE_11_0_SH_MASK_H 27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1 28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0 29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1 30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0 31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff 32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0 33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000 34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18 35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000 [all …]
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gc/
D	gc_10_3_0_offset.h	`23 #define _gc_10_3_0_OFFSET_HEADER 25 #define mmSQ_DEBUG_STS_GLOBAL … 26 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX … 27 #define mmSQ_DEBUG_STS_GLOBAL2 … 28 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX … 32 #define mmSDMA0_DEC_START … 33 #define mmSDMA0_DEC_START_BASE_IDX … 34 #define mmSDMA0_GLOBAL_TIMESTAMP_LO … 35 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX … 36 #define mmSDMA0_GLOBAL_TIMESTAMP_HI … [all …]`
D	gc_10_1_0_offset.h	`22 #define _gc_10_1_0_OFFSET_HEADER 24 #define mmSQ_DEBUG_STS_GLOBAL … 25 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX … 26 #define mmSQ_DEBUG_STS_GLOBAL2 … 27 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX … 31 #define mmSDMA0_DEC_START … 32 #define mmSDMA0_DEC_START_BASE_IDX … 33 #define mmSDMA0_PG_CNTL … 34 #define mmSDMA0_PG_CNTL_BASE_IDX … 35 #define mmSDMA0_PG_CTX_LO … [all …]`
D	gc_9_2_1_offset.h	`22 #define _gc_9_2_1_OFFSET_HEADER 24 #define mmSQ_DEBUG_STS_GLOBAL … 25 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX … 26 #define mmSQ_DEBUG_STS_GLOBAL2 … 27 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX … 28 #define mmSQ_DEBUG_STS_GLOBAL3 … 29 #define mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX … 33 #define mmGRBM_CNTL … 34 #define mmGRBM_CNTL_BASE_IDX … 35 #define mmGRBM_SKEW_CNTL … [all …]`
D	gc_9_1_offset.h	`22 #define _gc_9_1_OFFSET_HEADER 24 #define mmSQ_DEBUG_STS_GLOBAL … 25 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX … 26 #define mmSQ_DEBUG_STS_GLOBAL2 … 27 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX … 28 #define mmSQ_DEBUG_STS_GLOBAL3 … 29 #define mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX … 33 #define mmGRBM_CNTL … 34 #define mmGRBM_CNTL_BASE_IDX … 35 #define mmGRBM_SKEW_CNTL … [all …]`
D	gc_9_0_offset.h	`22 #define _gc_9_0_OFFSET_HEADER 24 #define mmSQ_DEBUG_STS_GLOBAL … 25 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX … 26 #define mmSQ_DEBUG_STS_GLOBAL2 … 27 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX … 28 #define mmSQ_DEBUG_STS_GLOBAL3 … 29 #define mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX … 33 #define mmGRBM_CNTL … 34 #define mmGRBM_CNTL_BASE_IDX … 35 #define mmGRBM_SKEW_CNTL … [all …]`
D	gc_10_3_0_default.h	`23 #define _gc_10_3_0_DEFAULT_HEADER 27 #define mmSDMA0_DEC_START_DEFAULT 0x00000000 28 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000 29 #define mmSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000 30 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000 31 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000 32 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000 33 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000 34 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050 35 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100 [all …]`
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/mmhub/
D	mmhub_9_4_1_offset.h	`22 #define _mmhub_9_4_1_OFFSET_HEADER 28 #define mmDAGB0_RDCLI0 … 29 #define mmDAGB0_RDCLI0_BASE_IDX … 30 #define mmDAGB0_RDCLI1 … 31 #define mmDAGB0_RDCLI1_BASE_IDX … 32 #define mmDAGB0_RDCLI2 … 33 #define mmDAGB0_RDCLI2_BASE_IDX … 34 #define mmDAGB0_RDCLI3 … 35 #define mmDAGB0_RDCLI3_BASE_IDX … 36 #define mmDAGB0_RDCLI4 … [all …]`
D	mmhub_9_1_offset.h	`22 #define _mmhub_9_1_OFFSET_HEADER 28 #define mmDAGB0_RDCLI0 … 29 #define mmDAGB0_RDCLI0_BASE_IDX … 30 #define mmDAGB0_RDCLI1 … 31 #define mmDAGB0_RDCLI1_BASE_IDX … 32 #define mmDAGB0_RDCLI2 … 33 #define mmDAGB0_RDCLI2_BASE_IDX … 34 #define mmDAGB0_RDCLI3 … 35 #define mmDAGB0_RDCLI3_BASE_IDX … 36 #define mmDAGB0_RDCLI4 … [all …]`
D	mmhub_9_3_0_offset.h	`22 #define _mmhub_9_3_0_OFFSET_HEADER 28 #define mmDAGB0_RDCLI0 … 29 #define mmDAGB0_RDCLI0_BASE_IDX … 30 #define mmDAGB0_RDCLI1 … 31 #define mmDAGB0_RDCLI1_BASE_IDX … 32 #define mmDAGB0_RDCLI2 … 33 #define mmDAGB0_RDCLI2_BASE_IDX … 34 #define mmDAGB0_RDCLI3 … 35 #define mmDAGB0_RDCLI3_BASE_IDX … 36 #define mmDAGB0_RDCLI4 … [all …]`
D	mmhub_1_0_offset.h	`22 #define _mmhub_1_0_OFFSET_HEADER 28 #define mmDAGB0_RDCLI0 … 29 #define mmDAGB0_RDCLI0_BASE_IDX … 30 #define mmDAGB0_RDCLI1 … 31 #define mmDAGB0_RDCLI1_BASE_IDX … 32 #define mmDAGB0_RDCLI2 … 33 #define mmDAGB0_RDCLI2_BASE_IDX … 34 #define mmDAGB0_RDCLI3 … 35 #define mmDAGB0_RDCLI3_BASE_IDX … 36 #define mmDAGB0_RDCLI4 … [all …]`
/Linux-v5.10/drivers/media/usb/dvb-usb/
D	af9005.h	12 #define _DVB_USB_AF9005_H_ 14 #define DVB_USB_LOG_PREFIX "af9005" 18 #define deb_info(args...) dprintk(dvb_usb_af9005_debug,0x01,args) 19 #define deb_xfer(args...) dprintk(dvb_usb_af9005_debug,0x02,args) 20 #define deb_rc(args...) dprintk(dvb_usb_af9005_debug,0x04,args) 21 #define deb_reg(args...) dprintk(dvb_usb_af9005_debug,0x08,args) 22 #define deb_i2c(args...) dprintk(dvb_usb_af9005_debug,0x10,args) 23 #define deb_fw(args...) dprintk(dvb_usb_af9005_debug,0x20,args) 28 #define FW_BULKOUT_SIZE 250 36 #define AF9005_OFDM_REG 0 [all …]
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
D	dcn_3_0_0_offset.h	`2 #define _dcn_3_0_0_OFFSET_HEADER 8 #define mmVGA_MEM_WRITE_PAGE_ADDR … 9 #define mmVGA_MEM_WRITE_PAGE_ADDR … 10 #define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX … 11 #define mmVGA_MEM_READ_PAGE_ADDR … 12 #define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX … 13 #define mmVGA_RENDER_CONTROL … 14 #define mmVGA_RENDER_CONTROL_BASE_IDX … 15 #define mmVGA_SEQUENCER_RESET_CONTROL … 16 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX … [all …]`
D	dcn_2_1_0_offset.h	`22 #define _dcn_2_1_0_OFFSET_HEADER 28 #define mmVGA_MEM_WRITE_PAGE_ADDR … 29 #define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX … 30 #define mmVGA_MEM_READ_PAGE_ADDR … 31 #define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX … 36 #define mmCRTC8_IDX … 37 #define mmCRTC8_IDX_BASE_IDX … 38 #define mmCRTC8_DATA … 39 #define mmCRTC8_DATA_BASE_IDX … 40 #define mmGENFC_WT … [all …]`
D	dcn_2_0_0_offset.h	`22 #define _dcn_2_0_0_OFFSET_HEADER 28 #define mmVGA_MEM_WRITE_PAGE_ADDR … 29 #define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX … 30 #define mmVGA_MEM_READ_PAGE_ADDR … 31 #define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX … 32 #define mmVGA_RENDER_CONTROL … 33 #define mmVGA_RENDER_CONTROL_BASE_IDX … 34 #define mmVGA_SEQUENCER_RESET_CONTROL … 35 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX … 36 #define mmVGA_MODE_CONTROL … [all …]`
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gmc/
D	gmc_7_1_sh_mask.h	`25 #define GMC_7_1_SH_MASK_H 27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1 28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2 30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4 32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10 [all …]`
D	gmc_8_1_sh_mask.h	`25 #define GMC_8_1_SH_MASK_H 27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1 28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2 30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4 32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10 [all …]`
/Linux-v5.10/drivers/media/dvb-frontends/drx39xyj/
D	drxj_map.h	`48 #define __DRXJ_MAP__H__ INCLUDED 56 #define ATV_COMM_EXEC__A 0xC00000 57 #define ATV_COMM_EXEC__W 2 58 #define ATV_COMM_EXEC__M 0x3 59 #define ATV_COMM_EXEC__PRE 0x0 60 #define ATV_COMM_EXEC_STOP 0x0 61 #define ATV_COMM_EXEC_ACTIVE 0x1 62 #define ATV_COMM_EXEC_HOLD 0x2 64 #define ATV_COMM_STATE__A 0xC00001 65 #define ATV_COMM_STATE__W 16 [all …]`
/Linux-v5.10/include/dt-bindings/clock/
D	exynos5433.h	`8 #define _DT_BINDINGS_CLOCK_EXYNOS5433_H 11 #define CLK_FOUT_ISP_PLL 1 12 #define CLK_FOUT_AUD_PLL 2 14 #define CLK_MOUT_AUD_PLL 10 15 #define CLK_MOUT_ISP_PLL 11 16 #define CLK_MOUT_AUD_PLL_USER_T 12 17 #define CLK_MOUT_MPHY_PLL_USER 13 18 #define CLK_MOUT_MFC_PLL_USER 14 19 #define CLK_MOUT_BUS_PLL_USER 15 20 #define CLK_MOUT_ACLK_HEVC_400 16 [all …]`
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/bif/
D	bif_3_0_sh_mask.h	24 #define BIF_3_0_SH_MASK_H 26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L 27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007 28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L 29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001 30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L 31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000 32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L 33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005 34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L [all …]
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/nbio/
D	nbio_7_0_default.h	22 #define _nbio_7_0_DEFAULT_HEADER 26 #define cfgNB_NBCFG0_NB_VENDOR_ID_DEFAULT 0x00000000 27 #define cfgNB_NBCFG0_NB_DEVICE_ID_DEFAULT 0x00000000 28 #define cfgNB_NBCFG0_NB_COMMAND_DEFAULT 0x00000000 29 #define cfgNB_NBCFG0_NB_STATUS_DEFAULT 0x00000000 30 #define cfgNB_NBCFG0_NB_REVISION_ID_DEFAULT 0x00000000 31 #define cfgNB_NBCFG0_NB_REGPROG_INF_DEFAULT 0x00000000 32 #define cfgNB_NBCFG0_NB_SUB_CLASS_DEFAULT 0x00000000 33 #define cfgNB_NBCFG0_NB_BASE_CODE_DEFAULT 0x00000000 34 #define cfgNB_NBCFG0_NB_CACHE_LINE_DEFAULT 0x00000000 [all …]
D	nbio_2_3_default.h	`22 #define _nbio_2_3_DEFAULT_HEADER 26 #define mmBIF_BX_PF_MM_INDEX_DEFAULT 0x00000000 27 #define mmBIF_BX_PF_MM_DATA_DEFAULT 0x00000000 28 #define mmBIF_BX_PF_MM_INDEX_HI_DEFAULT 0x00000000 32 #define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000 33 #define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000 34 #define mmPCIE_INDEX_DEFAULT 0x00000000 35 #define mmPCIE_DATA_DEFAULT 0x00000000 36 #define mmPCIE_INDEX2_DEFAULT 0x00000000 37 #define mmPCIE_DATA2_DEFAULT 0x00000000 [all …]`
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/oss/
D	oss_3_0_sh_mask.h	`25 #define OSS_3_0_SH_MASK_H 27 #define IH_VMID_0_LUT__PASID_MASK 0xffff 28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0 29 #define IH_VMID_1_LUT__PASID_MASK 0xffff 30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0 31 #define IH_VMID_2_LUT__PASID_MASK 0xffff 32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0 33 #define IH_VMID_3_LUT__PASID_MASK 0xffff 34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0 35 #define IH_VMID_4_LUT__PASID_MASK 0xffff [all …]`
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gca/
D	gfx_8_0_sh_mask.h	25 #define GFX_8_0_SH_MASK_H 27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff 28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0 29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff 30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0 31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff 32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0 33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff 34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0 35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 [all …]

12 3 4 5 6 7 8 9 10 >>...84