Home
last modified time | relevance | path

Searched +full:ddr +full:- +full:wb +full:- +full:channels (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.15/Documentation/devicetree/bindings/interrupt-controller/
Dqca,ath79-cpu-intc.txt3 On most SoC the IRQ controller need to flush the DDR FIFO before running
5 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
9 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc"
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
20 - qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
22 - qca,ddr-wb-channels: List of phandles to the write buffer channels for
23 each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
28 interrupt-controller {
29 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
[all …]
/Linux-v5.15/drivers/irqchip/
Dirq-ath79-cpu.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
7 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
18 #include <asm/mach-ath79/ath79.h>
27 * This array map the interrupt lines to the DDR write buffer channels.
31 -1, -1, -1, -1, -1, -1, -1, -1,
48 irq = fls(pending) - 1; in plat_irq_dispatch()
49 if (irq < ARRAY_SIZE(irq_wb_chan) && irq_wb_chan[irq] != -1) in plat_irq_dispatch()
63 node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells"); in ar79_cpu_intc_of_init()
70 node, "qca,ddr-wb-channel-interrupts", i, &irq); in ar79_cpu_intc_of_init()
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/memory-controllers/
Dqca,ath79-ddr-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller
10 - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
13 The DDR controller of the AR7xxx and AR9xxx families provides an interface to
14 flush the FIFO between various devices and the DDR. This is mainly used by
21 - items:
22 - const: qca,ar9132-ddr-controller
[all …]
/Linux-v5.15/arch/mips/boot/dts/qca/
Dar9132.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ath79-clk.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
22 cpuintc: interrupt-controller {
23 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
25 interrupt-controller;
26 #interrupt-cells = <1>;
[all …]
Dar9331.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ath79-clk.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
22 cpuintc: interrupt-controller {
23 compatible = "qca,ar7100-cpu-intc";
25 interrupt-controller;
26 #interrupt-cells = <1>;
[all …]