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/Linux-v6.1/Documentation/devicetree/bindings/perf/
Dfsl-imx-ddr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale(NXP) IMX8 DDR performance monitor
10 - Frank Li <frank.li@nxp.com>
15 - enum:
16 - fsl,imx8-ddr-pmu
17 - fsl,imx8m-ddr-pmu
18 - fsl,imx8mq-ddr-pmu
[all …]
Dmarvell-cn10k-ddr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/marvell-cn10k-ddr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell CN10K DDR performance monitor
10 - Bharat Bhushan <bbhushan2@marvell.com>
15 - enum:
16 - marvell,cn10k-ddr-pmu
22 - compatible
23 - reg
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/Linux-v6.1/drivers/perf/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
10 tristate "ARM CCI PMU driver"
14 Support for PMU events monitoring on the ARM CCI (Cache Coherent
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
45 tristate "Arm CMN-600 PMU support"
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Dfsl_imx8_ddr_perf.c1 // SPDX-License-Identifier: GPL-2.0
40 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
47 /* DDR Perf hardware feature */
52 unsigned int quirks; /* quirks needed for different DDR Perf core */
53 const char *identifier; /* system PMU identifier for userspace */
83 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
84 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
85 { .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data},
86 { .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data},
87 { .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data},
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Dmarvell_cn10k_ddr_pmu.c1 // SPDX-License-Identifier: GPL-2.0
48 /* Two dedicated event counters for DDR reads and writes */
54 * DO NOT change these event-id numbers, they are used to
125 struct pmu pmu; member
135 #define to_cn10k_ddr_pmu(p) container_of(p, struct cn10k_ddr_pmu, pmu)
144 return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id); in cn10k_ddr_pmu_event_show()
217 PMU_FORMAT_ATTR(event, "config:0-8");
233 struct cn10k_ddr_pmu *pmu = dev_get_drvdata(dev); in cn10k_ddr_perf_cpumask_show() local
235 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu)); in cn10k_ddr_perf_cpumask_show()
274 *event_bitmap = (1ULL << (eventid - 1)); in ddr_perf_get_event_bitmap()
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Dalibaba_uncore_drw_pmu.c1 // SPDX-License-Identifier: GPL-2.0
3 * Alibaba DDR Sub-System Driveway PMU driver
55 /* PMU EVENT SEL 0-3 are paired in 32-bit registers on a 4-byte stride */
57 /* counter 0-3 use sel0, counter 4-7 use sel1...*/
65 /* PMU COMMON COUNTER 0-15, are paired in 32-bit registers on a 4-byte stride */
105 struct pmu pmu; member
108 #define to_ali_drw_pmu(p) (container_of(p, struct ali_drw_pmu, pmu))
111 #define GET_DRW_EVENTID(event) FIELD_GET(DRW_CONFIG_EVENTID, (event)->attr.config)
120 return sprintf(buf, "%s\n", (char *)eattr->var); in ali_drw_pmu_format_show()
124 * PMU event attributes
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/Linux-v6.1/Documentation/admin-guide/perf/
Dalibaba_pmu.rst2 Alibaba's T-Head SoC Uncore Performance Monitoring Unit (PMU)
5 The Yitian 710, custom-built by Alibaba Group's chip development business,
6 T-Head, implements uncore PMU for performance and functional debugging to
9 DDR Sub-System Driveway (DRW) PMU Driver
14 channel is split into two independent sub-channels. The DDR Sub-System Driveway
15 implements separate PMUs for each sub-channel to monitor various performance
18 The Driveway PMU devices are named as ali_drw_<sys_base_addr> with perf.
19 For example, ali_drw_21000 and ali_drw_21080 are two PMU devices for two
20 sub-channels of the same channel in die 0. And the PMU device of die 1 is
23 Each sub-channel has 36 PMU counters in total, which is classified into
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Dhisi-pmu.rst2 HiSilicon SoC uncore Performance Monitoring Unit (PMU)
13 two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
15 HiSilicon SoC uncore PMU driver
16 -------------------------------
18 Each device PMU has separate registers for event counting, control and
19 interrupt, and the PMU driver shall register perf PMU drivers like L3C,
27 Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
28 name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>.
29 where "sccl-id" is the identifier of the SCCL and "index-id" is the index of
39 ID used to count the uncore PMU event.
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Dimx-ddr.rst2 Freescale i.MX8 DDR Performance Monitoring Unit (PMU)
21 in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/.
23 .. code-block:: bash
25 perf stat -a -e imx8_ddr0/cycles/ cmd
26 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
32 indicates whether PMU supports AXI ID filter or not; enhanced_filter indicates
33 whether PMU supports enhanced AXI ID filter or not. Value 0 for un-supported, and
38 --AXI_ID defines AxID matching value.
39 --AXI_MASKING defines which bits of AxID are meaningful for the matching.
[all …]
Dindex.rst1 .. SPDX-License-Identifier: GPL-2.0
10 hisi-pmu
11 hisi-pcie-pmu
12 hns3-pmu
13 imx-ddr
16 arm-ccn
17 arm-cmn
18 xgene-pmu
20 thunderx2-pmu
/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dimx8-ss-ddr.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019-2020 NXP
8 compatible = "simple-bus";
9 #address-cells = <1>;
10 #size-cells = <1>;
13 ddr_pmu0: ddr-pmu@5c020000 {
14 compatible = "fsl,imx8-ddr-pmu";
Dimx8dxl-ss-ddr.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 compatible = "fsl,imx8-ddr-pmu";
/Linux-v6.1/Documentation/devicetree/bindings/memory-controllers/
Drockchip,rk3399-dmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
20 Node to get DDR loading. Refer to
21 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
26 clock-names:
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/Linux-v6.1/drivers/perf/hisilicon/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "HiSilicon SoC PMU drivers"
7 Agent performance monitor and DDR Controller performance monitor.
10 tristate "HiSilicon PCIE PERF PMU"
13 Provide support for HiSilicon PCIe performance monitoring unit (PMU)
15 Adds the PCIe PMU into perf events system for monitoring latency,
19 tristate "HNS3 PERF PMU"
23 Provide support for HNS3 performance monitoring unit (PMU) RCiEP
25 Adds the HNS3 PMU into perf events system for monitoring latency,
/Linux-v6.1/drivers/devfreq/event/
Drockchip-dfi.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Lin Huang <hl@rock-chips.com>
8 #include <linux/devfreq-event.h>
46 * The dfi controller can monitor DDR load. It has an upper and lower threshold
48 * generated to indicate the DDR frequency should be changed.
63 void __iomem *dfi_regs = info->regs; in rockchip_dfi_start_hardware_counter()
67 /* get ddr type */ in rockchip_dfi_start_hardware_counter()
68 regmap_read(info->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val); in rockchip_dfi_start_hardware_counter()
75 /* set ddr type to dfi */ in rockchip_dfi_start_hardware_counter()
88 void __iomem *dfi_regs = info->regs; in rockchip_dfi_stop_hardware_counter()
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Decx-2000.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
12 model = "Calxeda ECX-2000";
13 compatible = "calxeda,ecx-2000";
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a15";
[all …]
Dhighbank.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
25 next-level-cache = <&L2>;
27 clock-names = "cpu";
[all …]
Dmeson8.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8-gpio.h>
9 #include <dt-bindings/power/meson8-power.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
20 #address-cells = <1>;
21 #size-cells = <0>;
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Dmeson8b.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/power/meson8-power.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
13 #include <dt-bindings/thermal/thermal.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
[all …]
/Linux-v6.1/tools/perf/pmu-events/
Dempty-pmu-events.c1 // SPDX-License-Identifier: GPL-2.0
3 * An empty pmu-events.c file used when there is no architecture json files in
8 #include "pmu-events/pmu-events.h"
10 #include "util/pmu.h"
31 .desc = "Memory cluster signals to block micro-op dispatch for any reason",
46 .pmu = "hisi_sccl,ddrc",
51 ….desc = "A cross-core snoop resulted from L3 Eviction which misses in some processor core. Unit: u…
53 .long_desc = "A cross-core snoop resulted from L3 Eviction which misses in some processor core",
54 .pmu = "uncore_cbox",
57 .name = "event-hyphen",
[all …]
/Linux-v6.1/drivers/devfreq/
Drk3399_dmc.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Lin Huang <hl@rock-chips.com>
7 #include <linux/arm-smccc.h>
12 #include <linux/devfreq-event.h>
74 unsigned long old_clk_rate = dmcfreq->rate; in rk3399_dmcfreq_target()
92 if (dmcfreq->rate == target_rate) in rk3399_dmcfreq_target()
95 mutex_lock(&dmcfreq->lock); in rk3399_dmcfreq_target()
98 * Ensure power-domain transitions don't interfere with ARM Trusted in rk3399_dmcfreq_target()
99 * Firmware power-domain idling. in rk3399_dmcfreq_target()
103 dev_err(dev, "Failed to block PMU: %d\n", err); in rk3399_dmcfreq_target()
[all …]
Dsun8i-a33-mbus.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // Copyright (C) 2020-2021 Samuel Holland <samuel@sholland.org>
25 #define MBUS_TMR_PERIOD(x) ((x) - 1)
28 #define MBUS_PMU_CFG_PERIOD(x) (((x) - 1) << 16)
107 /* Returns the peak transfer (in KiB) during any single PMU period. */ in sun8i_a33_mbus_get_peak_bw()
108 return readl_relaxed(priv->reg_mbus + MBUS_TOTAL_BWCR); in sun8i_a33_mbus_get_peak_bw()
115 /* All PMU counters are cleared on a disable->enable transition. */ in sun8i_a33_mbus_restart_pmu_counters()
117 priv->reg_mbus + MBUS_PMU_CFG); in sun8i_a33_mbus_restart_pmu_counters()
119 priv->reg_mbus + MBUS_PMU_CFG); in sun8i_a33_mbus_restart_pmu_counters()
127 * Nominal bandwidth (KiB per PMU period): in sun8i_a33_mbus_update_nominal_bw()
[all …]
/Linux-v6.1/tools/perf/tests/
Dpmu-events.c1 // SPDX-License-Identifier: GPL-2.0
3 #include "parse-events.h"
4 #include "pmu.h"
11 #include "../pmu-events/pmu-events.h"
15 #include "util/parse-events.h"
20 /* used for matching against events from generated pmu-events.c */
34 /* PMU which we should match against */
39 struct perf_pmu pmu; member
80 .desc = "Memory cluster signals to block micro-op dispatch for any reason",
84 .alias_long_desc = "Memory cluster signals to block micro-op dispatch for any reason",
[all …]
/Linux-v6.1/arch/arm/mach-imx/
Dmmdc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
59 #define to_mmdc_pmu(p) container_of(p, struct mmdc_pmu, pmu)
75 { .compatible = "fsl,imx6q-mmdc", .data = (void *)&imx6q_data},
76 { .compatible = "fsl,imx6qp-mmdc", .data = (void *)&imx6qp_data},
85 PMU_EVENT_ATTR_STRING(total-cycles, mmdc_pmu_total_cycles, "event=0x00")
86 PMU_EVENT_ATTR_STRING(busy-cycles, mmdc_pmu_busy_cycles, "event=0x01")
87 PMU_EVENT_ATTR_STRING(read-accesses, mmdc_pmu_read_accesses, "event=0x02")
88 PMU_EVENT_ATTR_STRING(write-accesses, mmdc_pmu_write_accesses, "event=0x03")
89 PMU_EVENT_ATTR_STRING(read-bytes, mmdc_pmu_read_bytes, "event=0x04")
90 PMU_EVENT_ATTR_STRING(read-bytes.unit, mmdc_pmu_read_bytes_unit, "MB");
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/interconnect/
Dqcom,msm8998-bwmon.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,msm8998-bwmon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
17 - Measuring the bandwidth between CPUs and Last Level Cache Controller -
19 - Measuring the bandwidth between Last Level Cache Controller and memory
20 (DDR) - called LLCC BWMON.
25 - items:
26 - enum:
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