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/Linux-v5.10/Documentation/devicetree/bindings/display/
Dallwinner,sun4i-a10-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Chen-Yu Tsai <wens@csie.org>
15 - Maxime Ripard <mripard@kernel.org>
20 - const: allwinner,sun4i-a10-hdmi
21 - const: allwinner,sun5i-a10s-hdmi
22 - const: allwinner,sun6i-a31-hdmi
23 - items:
[all …]
Dbrcm,bcm2835-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/brcm,bcm2835-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eric Anholt <eric@anholt.net>
14 const: brcm,bcm2835-hdmi
18 - description: HDMI register range
19 - description: HD register range
26 - description: The pixel clock
27 - description: The HDMI state machine clock
[all …]
Dbrcm,bcm2711-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/brcm,bcm2711-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eric Anholt <eric@anholt.net>
15 - brcm,bcm2711-hdmi0
16 - brcm,bcm2711-hdmi1
20 - description: HDMI controller register range
21 - description: DVP register range
22 - description: HDMI PHY register range
[all …]
Dst,stih4xx.txt3 - sti-vtg: video timing generator
5 - compatible: "st,vtg"
6 - reg: Physical base address of the IP registers and length of memory mapped region.
8 - interrupts : VTG interrupt number to the CPU.
9 - st,slave: phandle on a slave vtg
11 - sti-vtac: video timing advanced inter dye communication Rx and TX
13 - compatible: "st,vtac-main" or "st,vtac-aux"
14 - reg: Physical base address of the IP registers and length of memory mapped region.
15 - clocks: from common clock binding: handle hardware IP needed clocks, the
17 See ../clocks/clock-bindings.txt for details.
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/Linux-v5.10/drivers/gpu/drm/bridge/
Dsil-sii8620.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * Copyright (C) 2013-2014 Silicon Image, Inc.
243 /* LM DDC, default value: 0x80 */
252 /* DDC I2C Manual, default value: 0x03 */
263 /* DDC I2C Target Slave Address, default value: 0x00 */
267 /* DDC I2C Target Segment Address, default value: 0x00 */
270 /* DDC I2C Target Offset Address, default value: 0x00 */
273 /* DDC I2C Data In count #1, default value: 0x00 */
276 /* DDC I2C Data In count #2, default value: 0x00 */
280 /* DDC I2C Status, default value: 0x04 */
[all …]
/Linux-v5.10/drivers/gpu/drm/zte/
Dzx_vga.c1 // SPDX-License-Identifier: GPL-2.0-only
37 struct zx_vga_i2c *ddc; member
51 struct zx_vga_pwrctrl *pwrctrl = &vga->pwrctrl; in zx_vga_encoder_enable()
54 regmap_update_bits(pwrctrl->regmap, pwrctrl->reg, pwrctrl->mask, in zx_vga_encoder_enable()
55 pwrctrl->mask); in zx_vga_encoder_enable()
57 vou_inf_enable(VOU_VGA, encoder->crtc); in zx_vga_encoder_enable()
63 struct zx_vga_pwrctrl *pwrctrl = &vga->pwrctrl; in zx_vga_encoder_disable()
65 vou_inf_disable(VOU_VGA, encoder->crtc); in zx_vga_encoder_disable()
68 regmap_update_bits(pwrctrl->regmap, pwrctrl->reg, pwrctrl->mask, 0); in zx_vga_encoder_disable()
86 zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL, 0); in zx_vga_connector_get_modes()
[all …]
/Linux-v5.10/arch/arm64/boot/dts/amlogic/
Dmeson-gxbb-nanopi-k2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxbb.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
12 compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
21 stdout-path = "serial0:115200n8";
30 compatible = "gpio-leds";
32 led-stat {
33 label = "nanopi-k2:blue:stat";
35 default-state = "on";
[all …]
Dmeson-gxbb-odroidc2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxbb.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
14 compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
15 model = "Hardkernel ODROID-C2";
23 stdout-path = "serial0:115200n8";
31 usb_otg_pwr: regulator-usb-pwrs {
32 compatible = "regulator-fixed";
34 regulator-name = "USB_OTG_PWR";
[all …]
/Linux-v5.10/drivers/gpu/drm/sun4i/
Dsun4i_hdmi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
15 #include <media/cec-pin.h>
37 #define SUN4I_HDMI_VID_TIMING_X(x) ((((x) - 1) & GENMASK(11, 0)))
38 #define SUN4I_HDMI_VID_TIMING_Y(y) ((((y) - 1) & GENMASK(11, 0)) << 16)
135 #define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MAX (BIT(4) - 1)
138 #define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MAX (BIT(4) - 1)
143 #define SUN4I_HDMI_DDC_BYTE_COUNT_MAX (BIT(10) - 1)
187 /* DDC CLK bit fields are the same, but the formula is not */
226 /* DDC FIFO register offset */
[all …]
Dsun4i_hdmi_i2c.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
41 (hdmi->variant->ddc_fifo_thres_incl ? 0 : 1); in fifo_transfer()
50 if (regmap_field_read_poll_timeout(hdmi->field_ddc_int_status, reg, in fifo_transfer()
53 return -ETIMEDOUT; in fifo_transfer()
56 return -EIO; in fifo_transfer()
59 readsb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); in fifo_transfer()
61 writesb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); in fifo_transfer()
64 regmap_field_force_write(hdmi->field_ddc_int_status, in fifo_transfer()
76 if (hdmi->variant->ddc_fifo_has_dir) { in xfer_msg()
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Dsun5i-a10s.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/dma/sun4i-a10.h>
55 #address-cells = <1>;
56 #size-cells = <1>;
59 framebuffer-lcd0-hdmi {
60 compatible = "allwinner,simple-framebuffer",
61 "simple-framebuffer";
62 allwinner,pipeline = "de_be0-lcd0-hdmi";
70 display-engine {
[all …]
Dbcm2835-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 interrupt-parent = <&intc>;
12 compatible = "brcm,bcm2835-dma";
25 /* dma channel 11-14 share one irq */
32 interrupt-names = "dma0",
47 "dma-shared-all";
48 #dma-cells = <1>;
49 brcm,dma-channel-mask = <0x7f35>;
52 intc: interrupt-controller@7e00b200 {
53 compatible = "brcm,bcm2835-armctrl-ic";
[all …]
Dsun6i-a31.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
49 #include <dt-bindings/reset/sun6i-a31-ccu.h>
52 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <1>;
61 #address-cells = <1>;
[all …]
Dbcm2711.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
[all …]
Dimx6qdl-udoo.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 stdout-path = &uart2;
21 compatible = "gpio-backlight";
23 default-on;
27 gpio-poweroff {
28 compatible = "gpio-poweroff";
30 pinctrl-0 = <&pinctrl_power_off>;
31 pinctrl-names = "default";
41 * in reality it is a -20t (parallel) model,
43 * so it is equivalent to -19t model in drive
[all …]
Dda850-lcdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
5 /dts-v1/;
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
11 model = "DA850/AM1808/OMAP-L138 LCDK";
12 compatible = "ti,da850-lcdk", "ti,da850";
20 stdout-path = "serial2:115200n8";
28 reserved-memory {
29 #address-cells = <1>;
30 #size-cells = <1>;
[all …]
Dsun4i-a10.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/thermal/thermal.h>
45 #include <dt-bindings/dma/sun4i-a10.h>
46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #address-cells = <1>;
51 #size-cells = <1>;
52 interrupt-parent = <&intc>;
59 #address-cells = <1>;
60 #size-cells = <1>;
[all …]
Dsun7i-a20.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/dma/sun4i-a10.h>
48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <1>;
[all …]
Drk3288-phycore-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device tree file for Phytec phyCORE-RK3288 SoM
8 #include <dt-bindings/net/ti-dp83867.h>
13 compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288";
29 ext_gmac: external-gmac-clock {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <125000000>;
33 clock-output-names = "ext_gmac";
36 leds: user-leds {
[all …]
/Linux-v5.10/drivers/gpu/drm/bridge/synopsys/
Ddw-hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
19 #include <linux/dma-mapping.h>
22 #include <media/cec-notifier.h>
24 #include <uapi/linux/media-bus-format.h>
37 #include "dw-hdmi-audio.h"
38 #include "dw-hdmi-cec.h"
39 #include "dw-hdmi.h"
[all …]
/Linux-v5.10/drivers/gpu/drm/vc4/
Dvc4_hdmi.c1 // SPDX-License-Identifier: GPL-2.0-only
21 * and transfers them over an internal MAI (multi-channel audio
87 struct drm_info_node *node = (struct drm_info_node *)m->private; in vc4_hdmi_debugfs_regs()
88 struct vc4_hdmi *vc4_hdmi = node->info_ent->data; in vc4_hdmi_debugfs_regs()
91 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); in vc4_hdmi_debugfs_regs()
92 drm_print_regset32(&p, &vc4_hdmi->hd_regset); in vc4_hdmi_debugfs_regs()
114 reset_control_reset(vc4_hdmi->reset); in vc5_hdmi_reset()
127 if (vc4_hdmi->hpd_gpio) { in vc4_hdmi_connector_detect()
128 if (gpio_get_value_cansleep(vc4_hdmi->hpd_gpio) ^ in vc4_hdmi_connector_detect()
129 vc4_hdmi->hpd_active_low) in vc4_hdmi_connector_detect()
[all …]
/Linux-v5.10/drivers/gpu/drm/
Ddrm_dp_helper.c51 return link_status[r - DP_LANE0_1_STATUS]; in dp_link_status()
191 const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-"; in drm_dp_dump_access()
195 aux->name, offset, arrow, ret, min(ret, 20), buffer); in drm_dp_dump_access()
198 aux->name, offset, arrow, ret); in drm_dp_dump_access()
204 * The DisplayPort AUX channel is an abstraction to allow generic, driver-
208 * Transactions are described using a hardware-independent drm_dp_aux_msg
210 * Both native and I2C-over-AUX transactions are supported.
226 mutex_lock(&aux->hw_mutex); in drm_dp_dpcd_access()
235 if (ret != 0 && ret != -ETIMEDOUT) { in drm_dp_dpcd_access()
240 ret = aux->transfer(aux, &msg); in drm_dp_dpcd_access()
[all …]
/Linux-v5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-h6-pine-h64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 /dts-v1/;
6 #include "sun50i-h6.dtsi"
7 #include "sun50i-h6-cpu-opp.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
13 compatible = "pine64,pine-h64", "allwinner,sun50i-h6";
22 stdout-path = "serial0:115200n8";
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
28 clock-frequency = <32768>;
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/display/dc/
Ddc_link.h2 * Copyright 2012-14 Advanced Micro Devices, Inc.
87 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
127 struct ddc_service *ddc; member
172 * dc_get_link_at_index() - Return an enumerated dc_link.
180 return dc->links[link_index]; in dc_get_link_at_index()
188 for (i = 0; i < dc->link_count; i++) { in get_edp_link()
189 if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP) in get_edp_link()
190 return dc->links[i]; in get_edp_link()
203 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */
231 * boot - If this call is during initial boot.
[all …]
/Linux-v5.10/drivers/gpu/drm/i915/display/
Dintel_crt.c2 * Copyright © 2006-2007 Intel Corporation
91 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_crt_get_hw_state()
97 encoder->power_domain); in intel_crt_get_hw_state()
101 ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe); in intel_crt_get_hw_state()
103 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in intel_crt_get_hw_state()
110 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_crt_get_flags()
114 tmp = intel_de_read(dev_priv, crt->adpa_reg); in intel_crt_get_flags()
132 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); in intel_crt_get_config()
134 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); in intel_crt_get_config()
136 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_crt_get_config()
[all …]

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