| /Linux-v6.1/drivers/tty/hvc/ |
| D | Kconfig | 81 bool "ARM JTAG DCC console"
86 This console uses the JTAG DCC on ARM to create a console under the HVC
91 bool "Use DCC only on CPU core 0"
95 Some external debuggers, do not handle reads/writes from/to DCC on more
96 than one CPU core. Each core has its own DCC device registers, so when a
97 CPU core reads or writes from/to DCC, it only accesses its own DCC device.
99 write to the console, it might write to a different DCC.
102 shows the DCC output only from that core's DCC. The result is that
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| D | hvc_dcc.c | 14 #include <asm/dcc.h>
19 /* DCC Status Bits */
26 /* Lock to serialize access to DCC fifo */
55 EARLYCON_DECLARE(dcc, dcc_early_console_setup);
85 * Check if the DCC is enabled. If CONFIG_HVC_DCC_SERIALIZE_SMP is enabled,
95 * If we're not on core 0, but we previously confirmed that DCC is in hvc_dcc_check()
121 * Workqueue function that writes the output FIFO to the DCC on core 0.
130 /* While there's data in the output FIFO, write it to the DCC */ in dcc_put_work()
147 * Workqueue function that reads characters from DCC and puts them into the
156 * Read characters from DCC and put them into the input FIFO, as in dcc_get_work()
[all …]
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| /Linux-v6.1/net/netfilter/ |
| D | nf_conntrack_irc.c | 45 MODULE_DESCRIPTION("IRC (DCC) connection tracking helper");
53 MODULE_PARM_DESC(max_dcc_channels, "max number of expected DCC channels per "
56 MODULE_PARM_DESC(dcc_timeout, "timeout on for unestablished DCC channels");
64 /* tries to get the ip_addr and port out of a dcc command
66 * data pointer to first byte of DCC command data
67 * data_end pointer to last byte of dcc command data
68 * ip returns parsed ip of dcc command
69 * port returns parsed port of dcc command
175 /* strlen(" :\1DCC SENT t AAAAAAAA P\1\n")=26 in help()
186 /* then check that place only for the DCC command */ in help()
[all …]
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| D | nf_nat_irc.c | 25 MODULE_DESCRIPTION("IRC (DCC) NAT helper");
58 /* strlen("\1DCC CHAT chat AAAAAAAA P\1\n")=27 in help()
59 * strlen("\1DCC SCHAT chat AAAAAAAA P\1\n")=28 in help()
60 * strlen("\1DCC SEND F AAAAAAAA P S\1\n")=26 in help()
61 * strlen("\1DCC MOVE F AAAAAAAA P S\1\n")=26 in help()
62 * strlen("\1DCC TSEND F AAAAAAAA P S\1\n")=27 in help()
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| /Linux-v6.1/fs/f2fs/ |
| D | segment.c | 900 struct discard_cmd_control *dcc = SM_I(sbi)->dcc_info; in __create_discard_cmd() local
906 pend_list = &dcc->pend_list[plist_idx(len)]; in __create_discard_cmd()
922 atomic_inc(&dcc->discard_cmd_cnt); in __create_discard_cmd()
923 dcc->undiscard_blks += len; in __create_discard_cmd()
934 struct discard_cmd_control *dcc = SM_I(sbi)->dcc_info; in __attach_discard_cmd() local
940 rb_insert_color_cached(&dc->rb_node, &dcc->root, leftmost); in __attach_discard_cmd()
945 static void __detach_discard_cmd(struct discard_cmd_control *dcc, in __detach_discard_cmd() argument
949 atomic_sub(dc->queued, &dcc->queued_discard); in __detach_discard_cmd()
952 rb_erase_cached(&dc->rb_node, &dcc->root); in __detach_discard_cmd()
953 dcc->undiscard_blks -= dc->len; in __detach_discard_cmd()
[all …]
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| D | segment.h | 913 struct discard_cmd_control *dcc = SM_I(sbi)->dcc_info; in wake_up_discard_thread() local
920 mutex_lock(&dcc->cmd_lock); in wake_up_discard_thread()
922 if (i + 1 < dcc->discard_granularity) in wake_up_discard_thread()
924 if (!list_empty(&dcc->pend_list[i])) { in wake_up_discard_thread()
929 mutex_unlock(&dcc->cmd_lock); in wake_up_discard_thread()
933 dcc->discard_wake = 1; in wake_up_discard_thread()
934 wake_up_interruptible_all(&dcc->discard_wait_queue); in wake_up_discard_thread()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_plane.c | 155 return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier); in modifier_has_dcc()
243 /* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */ in fill_gfx9_tiling_info_from_modifier()
251 const struct dc_plane_dcc_param *dcc, in validate_dcc() argument
262 if (!dcc->enable) in validate_dcc()
285 if (dcc->independent_64b_blks == 0 && in validate_dcc()
298 struct dc_plane_dcc_param *dcc, in fill_gfx9_plane_attributes_from_modifiers() argument
313 dcc->enable = 1; in fill_gfx9_plane_attributes_from_modifiers()
314 dcc->meta_pitch = afb->base.pitches[1]; in fill_gfx9_plane_attributes_from_modifiers()
315 dcc->independent_64b_blks = independent_64b_blks; in fill_gfx9_plane_attributes_from_modifiers()
318 dcc->dcc_ind_blk = hubp_ind_block_64b_no_128bcl; in fill_gfx9_plane_attributes_from_modifiers()
[all …]
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_hubp.c | 355 struct dc_plane_dcc_param *dcc) in hubp3_dcc_control_sienna_cichlid() argument
360 PRIMARY_SURFACE_DCC_EN, dcc->enable, in hubp3_dcc_control_sienna_cichlid()
361 PRIMARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk, in hubp3_dcc_control_sienna_cichlid()
362 PRIMARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c, in hubp3_dcc_control_sienna_cichlid()
363 SECONDARY_SURFACE_DCC_EN, dcc->enable, in hubp3_dcc_control_sienna_cichlid()
364 SECONDARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk, in hubp3_dcc_control_sienna_cichlid()
365 SECONDARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c); in hubp3_dcc_control_sienna_cichlid()
405 struct dc_plane_dcc_param *dcc, in hubp3_program_surface_config() argument
411 hubp3_dcc_control_sienna_cichlid(hubp, dcc); in hubp3_program_surface_config()
413 hubp2_program_size(hubp, format, plane_size, dcc); in hubp3_program_surface_config()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn201/ |
| D | dcn201_hubp.c | 48 struct dc_plane_dcc_param *dcc, in hubp201_program_surface_config() argument
52 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp201_program_surface_config()
54 hubp1_program_size(hubp, format, plane_size, dcc); in hubp201_program_surface_config()
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| /Linux-v6.1/drivers/bus/ |
| D | vexpress-config.c | 108 u32 *position, u32 *dcc) in vexpress_config_get_topo() argument
116 vexpress_config_find_prop(node, "arm,vexpress,dcc", dcc); in vexpress_config_get_topo()
257 u32 site, position, dcc; in vexpress_syscfg_regmap_init() local
261 &position, &dcc); in vexpress_syscfg_regmap_init()
301 func, site, position, dcc, in vexpress_syscfg_regmap_init()
304 func->template[i] = SYS_CFGCTRL_DCC(dcc); in vexpress_syscfg_regmap_init()
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| /Linux-v6.1/arch/arm/boot/dts/ |
| D | vexpress-v2p-ca5s.dts | 143 dcc {
201 temp-dcc {
202 /* DCC internal operating temperature */
205 label = "DCC";
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| D | vexpress-v2p-ca15-tc1.dts | 141 dcc {
217 temp-dcc {
218 /* DCC internal temperature */
221 label = "DCC";
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| D | vexpress-v2p-ca15_a7.dts | 252 dcc {
373 temp-dcc {
374 /* DCC internal temperature */
377 label = "DCC";
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| /Linux-v6.1/arch/arm64/include/asm/ |
| D | dcc.h | 6 * not speculative read the DCC status before executing the read or write
10 * and instead reads the DCC register every time.
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| /Linux-v6.1/arch/arm64/boot/dts/xilinx/ |
| D | zynqmp-zc1275-revA.dts | 22 serial1 = &dcc;
37 &dcc {
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| D | zynqmp-zc1254-revA.dts | 22 serial1 = &dcc;
37 &dcc {
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| D | zynqmp-zc1232-revA.dts | 21 serial1 = &dcc;
36 &dcc {
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| /Linux-v6.1/drivers/irqchip/ |
| D | irq-gic-realview.c | 62 /* new irq mode with no DCC */ in realview_gic_of_init()
69 pr_info("RealView GIC: set up interrupt controller to NEW mode, no DCC\n"); in realview_gic_of_init()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hubp.c | 167 struct dc_plane_dcc_param *dcc) in hubp1_program_size() argument
180 meta_pitch = dcc->meta_pitch - 1; in hubp1_program_size()
182 meta_pitch_c = dcc->meta_pitch_c - 1; in hubp1_program_size()
185 meta_pitch = dcc->meta_pitch - 1; in hubp1_program_size()
190 if (!dcc->enable) { in hubp1_program_size()
541 struct dc_plane_dcc_param *dcc, in hubp1_program_surface_config() argument
545 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp1_program_surface_config()
547 hubp1_program_size(hubp, format, plane_size, dcc); in hubp1_program_surface_config()
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| /Linux-v6.1/drivers/gpu/drm/i915/gt/ |
| D | intel_ggtt_fencing.c | 666 u32 dcc = intel_uncore_read(uncore, DCC); in detect_bit_6_swizzle() local
670 * determined by DCC. For single-channel, neither the CPU in detect_bit_6_swizzle()
677 switch (dcc & DCC_ADDRESSING_MODE_MASK) { in detect_bit_6_swizzle()
684 if (dcc & DCC_CHANNEL_XOR_DISABLE) { in detect_bit_6_swizzle()
691 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) { in detect_bit_6_swizzle()
710 if (dcc == 0xffffffff) { in detect_bit_6_swizzle()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| D | dcn_calcs.c | 320 * this method requires us to always re-calculate watermark when dcc change in pipe_ctx_to_e2e_pipe_params()
323 input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0; in pipe_ctx_to_e2e_pipe_params()
326 * allow us to disable dcc on the fly without re-calculating WM in pipe_ctx_to_e2e_pipe_params()
328 * extra overhead for DCC is quite small. for 1080p WM without in pipe_ctx_to_e2e_pipe_params()
329 * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us) in pipe_ctx_to_e2e_pipe_params()
333 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> in pipe_ctx_to_e2e_pipe_params()
337 input->src.meta_pitch = pipe->plane_state->dcc.meta_pitch; in pipe_ctx_to_e2e_pipe_params()
990 * this method requires us to always re-calculate watermark when dcc change in dcn_validate_bandwidth()
993 v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no; in dcn_validate_bandwidth()
996 * allow us to disable dcc on the fly without re-calculating WM in dcn_validate_bandwidth()
[all …]
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hubp.c | 330 struct dc_plane_dcc_param *dcc) in hubp2_program_size() argument
348 meta_pitch = dcc->meta_pitch - 1; in hubp2_program_size()
350 meta_pitch_c = dcc->meta_pitch_c - 1; in hubp2_program_size()
353 meta_pitch = dcc->meta_pitch - 1; in hubp2_program_size()
358 if (!dcc->enable) { in hubp2_program_size()
540 struct dc_plane_dcc_param *dcc, in hubp2_program_surface_config() argument
546 hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp2_program_surface_config()
548 hubp2_program_size(hubp, format, plane_size, dcc); in hubp2_program_surface_config()
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| /Linux-v6.1/include/uapi/drm/ |
| D | drm_fourcc.h | 1350 * without DCC:
1353 * with DCC & without DCC_RETILE:
1355 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
1357 * with DCC & DCC_RETILE:
1359 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
1360 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
1370 * 13 DCC
1419 /* Whether DCC compression is enabled. */
1424 * Whether to include two DCC surfaces, one which is rb & pipe aligned, and
1442 * DCC supports embedding some clear colors directly in the DCC surface.
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/sound/ |
| D | mt6359.yaml | 38 - 3 # DCC - analog mic with direct couping
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| /Linux-v6.1/Documentation/devicetree/bindings/arm/ |
| D | arm,vexpress-juno.yaml | 129 arm,vexpress,dcc:
130 description: When describing tiles consisting of more than one DCC, its
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