| /Linux-v6.6/Documentation/devicetree/bindings/iio/dac/ |
| D | adi,ad5755.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD5755 Multi-Channel DAC
10 - Sean Nyekjaer <sean.nyekjaer@prevas.dk>
15 - adi,ad5755
16 - adi,ad5755-1
17 - adi,ad5757
18 - adi,ad5735
19 - adi,ad5737
[all …]
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| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_dccg.c | 35 (dccg_dcn->regs->reg)
39 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
42 dccg_dcn->base.ctx
44 dccg->ctx->logger
50 if (dccg->dpp_clock_gated[dpp_inst]) { in dccg31_update_dpp_dto()
58 if (dccg->ref_dppclk && req_dppclk) { in dccg31_update_dpp_dto()
59 int ref_dppclk = dccg->ref_dppclk; in dccg31_update_dpp_dto()
60 int modulo, phase; in dccg31_update_dpp_dto() local
62 // phase / modulo = dpp pipe clk / dpp global clk in dccg31_update_dpp_dto()
64 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg31_update_dpp_dto()
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| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | dcn30_fpu.c | 2 * Copyright 2020-2021 Advanced Micro Devices, Inc.
37 optc1->tg_regs->reg
40 optc1->base.ctx
44 optc1->tg_shift->field_name, optc1->tg_mask->field_name
186 double ratio, modulo, phase; in optc3_fpu_set_vrr_m_const() local
193 * VOTAL_MAX - VTOTAL_MIN = 1 in optc3_fpu_set_vrr_m_const()
201 * of lines in a frame - 1'. in optc3_fpu_set_vrr_m_const()
213 optc->funcs->set_vtotal_min_max(optc, 0, 0); in optc3_fpu_set_vrr_m_const()
223 ratio = vtotal_max - vtotal_avg; in optc3_fpu_set_vrr_m_const()
224 modulo = 65536.0 * 65536.0 - 1.0; /* 2^32 - 1 */ in optc3_fpu_set_vrr_m_const()
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| /Linux-v6.6/drivers/regulator/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
38 managed regulators and simple non-configurable regulators.
65 They provide two I2C-controlled DC/DC step-down converters with
85 tristate "Active-semi act8865 voltage regulator"
90 This driver controls a active-semi act8865 voltage output
94 tristate "Active-semi ACT8945A voltage regulator"
97 This driver controls a active-semi ACT8945A voltage regulator
98 via I2C bus. The ACT8945A features three step-down DC/DC converters
99 and four low-dropout linear regulators, along with a ActivePath
110 tristate "Freescale i.MX on-chip ANATOP LDO regulators"
[all …]
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| /Linux-v6.6/Documentation/devicetree/bindings/ |
| D | trivial-devices.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
27 spi-max-frequency: true
31 - enum:
33 - acbel,fsg032
34 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
35 - ad,ad7414
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| /Linux-v6.6/drivers/tty/ |
| D | nozomi.c | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * nozomi.c -- HSDPA driver Broadband Wireless Data Card - Globe Trotter
18 * --------------------------------------------------------------------------
25 * --------------------------------------------------------------------------
78 if (tbuf[data_len - 2] == '\r') \
79 tbuf[data_len - 2] = 'r'; \
148 F32_2 = 2048, /* 512 bytes downlink + uplink * 2 -> 2048 */
149 F32_8 = 8192, /* 3072 bytes downl. + 1024 bytes uplink * 2 -> 8192 */
173 CTRL_ERROR = -1,
183 PORT_ERROR = -1,
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| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer.c | 63 hws->ctx
65 hws->regs->reg
69 hws->shifts->field_name, hws->masks->field_name
84 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in print_microsec()
93 void dcn10_lock_all_pipes(struct dc *dc, in dcn10_lock_all_pipes() argument
102 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
103 old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in dcn10_lock_all_pipes()
104 pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn10_lock_all_pipes()
105 tg = pipe_ctx->stream_res.tg; in dcn10_lock_all_pipes()
111 if (pipe_ctx->top_pipe || in dcn10_lock_all_pipes()
[all …]
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| D | dcn10_dpp_dscl.c | 44 dpp->tf_regs->reg
47 dpp->base.ctx
51 dpp->tf_shift->field_name, dpp->tf_mask->field_name
65 /* Autocal calculate the scaling ratio and initial phase and the
101 return -1; /* Unsupported */ in dpp1_dscl_get_pixel_depth_val()
130 if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { in dpp1_dscl_get_dscl_mode()
132 if (data->format == PIXEL_FORMAT_FP16) in dpp1_dscl_get_dscl_mode()
136 if (data->ratios.horz.value == one in dpp1_dscl_get_dscl_mode()
137 && data->ratios.vert.value == one in dpp1_dscl_get_dscl_mode()
138 && data->ratios.horz_c.value == one in dpp1_dscl_get_dscl_mode()
[all …]
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| /Linux-v6.6/drivers/iio/dac/ |
| D | ad5755.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * AD5755, AD5755-1, AD5757, AD5735, AD5737 Digital to analog converters driver
128 * struct ad5755_platform_data - AD5755 DAC driver platform data
129 * @ext_dc_dc_compenstation_resistor: Whether an external DC-DC converter
131 * @dc_dc_phase: DC-DC converter phase.
132 * @dc_dc_freq: DC-DC converter frequency.
133 * @dc_dc_maxv: DC-DC maximum allowed boost voltage.
162 * struct ad5755_chip_info - chip specific information
174 * struct ad5755_state - driver instance specific data
257 st->data[0].d32 = cpu_to_be32((reg << 16) | val); in ad5755_write_unlocked()
[all …]
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| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/dcn314/ |
| D | dcn314_dccg.c | 1 // SPDX-License-Identifier: MIT
37 (dccg_dcn->regs->reg)
41 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
44 dccg_dcn->base.ctx
46 dccg->ctx->logger
203 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
210 int req_dtbclk_khz = params->pixclk_khz / 4; in dccg314_set_dtbclk_dto()
212 if (params->ref_dtbclk_khz && req_dtbclk_khz) { in dccg314_set_dtbclk_dto()
213 uint32_t modulo, phase; in dccg314_set_dtbclk_dto() local
215 // phase / modulo = dtbclk / dtbclk ref in dccg314_set_dtbclk_dto()
[all …]
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| /Linux-v6.6/Documentation/devicetree/bindings/display/ |
| D | solomon,ssd1307fb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Maxime Ripard <mripard@kernel.org>
11 - Javier Martinez Canillas <javierm@redhat.com>
17 - enum:
18 - solomon,ssd1305fb-i2c
19 - solomon,ssd1306fb-i2c
20 - solomon,ssd1307fb-i2c
21 - solomon,ssd1309fb-i2c
[all …]
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| /Linux-v6.6/Documentation/hwmon/ |
| D | ucd9200.rst | 11 Addresses scanned: -
15 - http://focus.ti.com/lit/ds/symlink/ucd9220.pdf
16 - http://focus.ti.com/lit/ds/symlink/ucd9222.pdf
17 - http://focus.ti.com/lit/ds/symlink/ucd9224.pdf
18 - http://focus.ti.com/lit/ds/symlink/ucd9240.pdf
19 - http://focus.ti.com/lit/ds/symlink/ucd9244.pdf
20 - http://focus.ti.com/lit/ds/symlink/ucd9246.pdf
21 - http://focus.ti.com/lit/ds/symlink/ucd9248.pdf
23 Author: Guenter Roeck <linux@roeck-us.net>
27 -----------
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| D | ltc2978.rst | 10 Addresses scanned: -
18 Addresses scanned: -
26 Addresses scanned: -
34 Addresses scanned: -
42 Addresses scanned: -
52 Addresses scanned: -
60 Addresses scanned: -
68 Addresses scanned: -
76 Addresses scanned: -
84 Addresses scanned: -
[all …]
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| D | xdpe12284.rst | 1 .. SPDX-License-Identifier: GPL-2.0
25 -----------
27 This driver implements support for Infineon Multi-phase XDPE112 and XDPE122
32 - Intel VR13 and VR13HC rev 1.3, IMVP8 rev 1.2 and IMPVP9 rev 1.3 DC-DC
34 - Intel SVID rev 1.9. protocol.
35 - PMBus rev 1.3 interface.
41 - VR12.0 mode, 5-mV DAC - 0x01.
42 - VR12.5 mode, 10-mV DAC - 0x02.
43 - IMVP9 mode, 5-mV DAC - 0x03.
44 - AMD mode 6.25mV - 0x10.
[all …]
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| /Linux-v6.6/drivers/hwmon/pmbus/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
37 be called acbel-fsg032.
55 and ADM1294 Hot-Swap Controller and Digital Power Monitors.
67 be called bel-pfe.
70 tristate "BluTek BPA-RS600 Power Supplies"
73 BPA-RS600 Power Supplies.
76 be called bpa-rs600.
79 tristate "Delta AHE-50DC fan control module"
82 the integrated fan control module of the Delta AHE-50DC
86 will be called delta-ahe50dc-fan.
[all …]
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| D | delta-ahe50dc-fan.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Delta AHE-50DC power shelf fan control module driver
29 return value == PMBUS_CLEAR_FAULTS ? -EOPNOTSUPP : -ENODATA; in ahe50dc_fan_write_byte()
32 static int ahe50dc_fan_read_word_data(struct i2c_client *client, int page, int phase, int reg) in ahe50dc_fan_read_word_data() argument
34 /* temp1 in (virtual) page 1 is remapped to mfr-specific temp4 */ in ahe50dc_fan_read_word_data()
38 return -EOPNOTSUPP; in ahe50dc_fan_read_word_data()
62 return -ENODATA; in ahe50dc_fan_read_word_data()
64 return -EOPNOTSUPP; in ahe50dc_fan_read_word_data()
101 client->dev.platform_data = &ahe50dc_fan_data; in ahe50dc_fan_probe()
112 { .compatible = "delta,ahe50dc-fan" },
[all …]
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| /Linux-v6.6/drivers/gpu/drm/tegra/ |
| D | dc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
32 #include "dc.h"
43 stats->frames = 0; in tegra_dc_stats_reset()
44 stats->vblank = 0; in tegra_dc_stats_reset()
45 stats->underflow = 0; in tegra_dc_stats_reset()
46 stats->overflow = 0; in tegra_dc_stats_reset()
50 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) in tegra_dc_readl_active() argument
54 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
55 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
[all …]
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| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clock_source.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
41 (clk_src->regs->reg)
44 clk_src->base.ctx
50 clk_src->cs_shift->field_name, clk_src->cs_mask->field_name
72 ss_parm = clk_src->dvi_ss_params; in get_ss_data_entry()
73 entrys_num = clk_src->dvi_ss_params_cnt; in get_ss_data_entry()
77 ss_parm = clk_src->hdmi_ss_params; in get_ss_data_entry()
78 entrys_num = clk_src->hdmi_ss_params_cnt; in get_ss_data_entry()
82 ss_parm = clk_src->lvds_ss_params; in get_ss_data_entry()
83 entrys_num = clk_src->lvds_ss_params_cnt; in get_ss_data_entry()
[all …]
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| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_dccg.c | 36 (dccg_dcn->regs->reg)
40 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
43 dccg_dcn->base.ctx
45 dccg->ctx->logger
51 if (dccg->ref_dppclk && req_dppclk) { in dccg2_update_dpp_dto()
52 int ref_dppclk = dccg->ref_dppclk; in dccg2_update_dpp_dto()
53 int modulo, phase; in dccg2_update_dpp_dto() local
55 // phase / modulo = dpp pipe clk / dpp global clk in dccg2_update_dpp_dto()
57 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg2_update_dpp_dto()
59 if (phase > 0xff) { in dccg2_update_dpp_dto()
[all …]
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| /Linux-v6.6/drivers/media/i2c/ |
| D | saa711x_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * saa711x - Philips SAA711x video decoder register specifications
10 /* Video Decoder - Frontend part */
16 /* Video Decoder - Decoder part */
112 /* Horizontal phase scaling */
159 /* Horizontal phase scaling */
196 /* SAA7113 bit-masks */
230 /* Video Decoder - Frontend part: R_01_INC_DELAY to R_05_INPUT_CNTL_4 */
242 /* Video Decoder - Decoder part: R_06_H_SYNC_START to R_1F_STATUS_BYTE_2_VD_DEC */
297 /* 0x20 to 0x22 - Reserved */
[all …]
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| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| D | dcn32_fpu.c | 1 // SPDX-License-Identifier: MIT
176 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn32_build_wm_range_table_fpu()
177 double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us; in dcn32_build_wm_range_table_fpu()
178 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; in dcn32_build_wm_range_table_fpu()
179 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn32_build_wm_range_table_fpu()
181 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; in dcn32_build_wm_range_table_fpu()
182 uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
184 …uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_m… in dcn32_build_wm_range_table_fpu()
190 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_… in dcn32_build_wm_range_table_fpu()
192 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_pa… in dcn32_build_wm_range_table_fpu()
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| /Linux-v6.6/Documentation/RCU/Design/Memory-Ordering/ |
| D | TreeRCU-callback-invocation.svg | 1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
2 <!-- Creator: fig2dev Version 3.2 Patchlevel 5e -->
4 <!-- CreationDate: Wed Dec 9 17:35:03 2015 -->
6 <!-- Magnification: 2.000 -->
9 xmlns:dc="http://purl.org/dc/elements/1.1/"
11 xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
14 xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
18 viewBox="-44 -44 7874.1949 6244.9802"
22 sodipodi:docname="TreeRCU-callback-invocation.svg">
28 <dc:format>image/svg+xml</dc:format>
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| /Linux-v6.6/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| D | smu13_driver_if_v13_0_0.h | 175 SVI_PSI_0, // Full phase count (default)
176 SVI_PSI_1, // Phase count 1st level
177 SVI_PSI_2, // Phase count 2nd level
178 SVI_PSI_3, // Single phase operation + active diode emulation
179 SVI_PSI_4, // Single phase operation + passive diode emulation *optional*
182 SVI_PSI_7, // Automated phase shedding and diode emulation
503 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM
506 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
509 uint16_t FoptimalDc; //Foptimal frequency in DC power mode.
954 …TLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in DC mode. Multiple limit…
[all …]
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| D | smu13_driver_if_v13_0_7.h | 176 SVI_PSI_0, // Full phase count (default)
177 SVI_PSI_1, // Phase count 1st level
178 SVI_PSI_2, // Phase count 2nd level
179 SVI_PSI_3, // Single phase operation + active diode emulation
180 SVI_PSI_4, // Single phase operation + passive diode emulation *optional*
183 SVI_PSI_7, // Automated phase shedding and diode emulation
504 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM
507 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
510 uint16_t FoptimalDc; //Foptimal frequency in DC power mode.
963 …TLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in DC mode. Multiple limit…
[all …]
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| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_transform_v.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
28 #include "dc.h"
34 xfm->ctx->logger
53 luma_viewport->x = scl_data->viewport.x - scl_data->viewport.x % 2; in calculate_viewport()
54 luma_viewport->y = scl_data->viewport.y - scl_data->viewport.y % 2; in calculate_viewport()
55 luma_viewport->width = in calculate_viewport()
56 scl_data->viewport.width - scl_data->viewport.width % 2; in calculate_viewport()
57 luma_viewport->height = in calculate_viewport()
58 scl_data->viewport.height - scl_data->viewport.height % 2; in calculate_viewport()
59 chroma_viewport->x = luma_viewport->x; in calculate_viewport()
[all …]
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