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/Linux-v6.1/drivers/auxdisplay/
Dhd44780.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2000-2008, Willy Tarreau <w@1wt.eu>
6 * Copyright (C) 2016-2017 Glider bvba
38 struct gpio_desc *pins[PIN_NUM]; member
43 struct hd44780_common *hdc = lcd->drvdata; in hd44780_backlight()
44 struct hd44780 *hd = hdc->hd44780; in hd44780_backlight()
46 if (hd->pins[PIN_CTRL_BL]) in hd44780_backlight()
47 gpiod_set_value_cansleep(hd->pins[PIN_CTRL_BL], on); in hd44780_backlight()
52 /* Maintain the data during 20 us before the strobe */ in hd44780_strobe_gpio()
55 gpiod_set_value_cansleep(hd->pins[PIN_CTRL_E], 1); in hd44780_strobe_gpio()
[all …]
Dpanel.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2000-2008, Willy Tarreau <w@1wt.eu>
5 * Copyright (C) 2016-2017 Glider bvba
10 * The LCD module may either be an HD44780-like 8-bit parallel LCD, or a 1-bit
11 * serial module compatible with Samsung's KS0074. The pins may be connected in
14 * The keypad consists in a matrix of push buttons connecting input pins to
15 * data output pins or to the ground. The combinations have to be hard-coded
22 * - the initialization/deinitialization process is very dirty and should
26 * - document 24 keys keyboard (3 rows of 8 cols, 32 diodes + 2 inputs)
27 * - make the LCD a part of a virtual screen of Vx*Vy
[all …]
/Linux-v6.1/arch/arm64/boot/dts/qcom/
Dmsm8916-pins.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
8 blsp1_uart1_default: blsp1-uart1-default {
10 pins = "gpio0", "gpio1", "gpio2", "gpio3";
13 drive-strength = <16>;
14 bias-disable;
17 blsp1_uart1_sleep: blsp1-uart1-sleep {
18 pins = "gpio0", "gpio1", "gpio2", "gpio3";
21 drive-strength = <2>;
22 bias-pull-down;
[all …]
Dsc7180-idp.dts1 // SPDX-License-Identifier: BSD-3-Clause
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
12 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
19 compatible = "qcom,sc7180-idp", "qcom,sc7180";
29 stdout-path = "serial0:115200n8";
41 /delete-node/ &hyp_mem;
42 /delete-node/ &xbl_mem;
43 /delete-node/ &aop_mem;
[all …]
Dsc7280.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
11 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
[all …]
Dsc7180-trogdor.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/gpio-keys.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include <dt-bindings/sound/sc7180-lpass.h>
21 thermal-zones {
22 charger_thermal: charger-thermal {
23 polling-delay-passive = <0>;
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Ds3c2416-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include "s3c2410-pinctrl.h"
15 gpa: gpa-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
20 gpb: gpb-gpio-bank {
21 gpio-controller;
22 #gpio-cells = <2>;
25 gpc: gpc-gpio-bank {
26 gpio-controller;
[all …]
Ds3c64xx-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 * - pin control-related definitions
8 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
12 #include "s3c64xx-pinctrl.h"
19 gpa: gpa-gpio-bank {
20 gpio-controller;
21 #gpio-cells = <2>;
22 interrupt-controller;
23 #interrupt-cells = <2>;
26 gpb: gpb-gpio-bank {
[all …]
Dkirkwood-nsa320.dts1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (c) 2014, Adam Baker <linux@baker-net.org.uk>
9 /dts-v1/;
11 #include "kirkwood-nsa3x0-common.dtsi"
15 compatible = "zyxel,nsa320", "marvell,kirkwood-88f6281", "marvell,kirkwood";
24 stdout-path = &uart0;
28 pinctrl: pin-controller@10000 {
29 pinctrl-names = "default";
31 /* SATA Activity and Present pins are not connected */
32 pmx_sata0: pmx-sata0 {
[all …]
Dexynos4210-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
5 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2011-2012 Linaro Ltd.
10 * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
14 #include "exynos-pinctrl.h"
17 gpa0: gpa0-gpio-bank {
18 gpio-controller;
19 #gpio-cells = <2>;
21 interrupt-controller;
[all …]
Dqcom-apq8064-pins.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 sdc4_gpios: sdc4-gpios {
6 pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
11 sdcc1_pins: sdcc1-pin-active {
13 pins = "sdc1_clk";
14 drive-strengh = <16>;
15 bias-disable;
19 pins = "sdc1_cmd";
20 drive-strengh = <10>;
21 bias-pull-up;
[all …]
Dexynos4412-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4412 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos4412 SoCs pin-mux and pin-config optiosn are listed as device
12 #include "exynos-pinctrl.h"
16 samsung,pins = #_pin; \
17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
22 gpa0: gpa0-gpio-bank {
23 gpio-controller;
24 #gpio-cells = <2>;
[all …]
Dat91sam9x5.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
11 #include <dt-bindings/dma/at91.h>
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/clock/at91.h>
16 #include <dt-bindings/mfd/at91-usart.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
[all …]
/Linux-v6.1/drivers/pinctrl/samsung/
Dpinctrl-s3c64xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 // S3C64xx specific support for pinctrl-samsung driver.
7 // Based on pinctrl-exynos.c, please see the file for original copyrights.
24 #include "pinctrl-samsung.h"
96 #define PIN_BANK_4BIT(pins, reg, id) \ argument
100 .nr_pins = pins, \
105 #define PIN_BANK_4BIT_EINTG(pins, reg, id, eoffs) \ argument
109 .nr_pins = pins, \
112 .eint_mask = (1 << (pins)) - 1, \
117 #define PIN_BANK_4BIT_EINTW(pins, reg, id, eoffs, emask) \ argument
[all …]
Dpinctrl-exynos.h1 /* SPDX-License-Identifier: GPL-2.0+ */
54 #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ argument
58 .nr_pins = pins, \
63 #define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \ argument
67 .nr_pins = pins, \
73 #define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \ argument
77 .nr_pins = pins, \
83 #define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \ argument
87 .nr_pins = pins, \
93 #define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs) \ argument
[all …]
Dpinctrl-samsung.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
65 * enum eint_type - possible external interrupt types.
71 * Samsung GPIO controller groups all the available pins into banks. The pins
85 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
91 .pins = p, \
116 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
[all …]
/Linux-v6.1/drivers/pinctrl/renesas/
Dpinctrl-rzv2m.c1 // SPDX-License-Identifier: GPL-2.0
18 #include <linux/pinctrl/pinconf-generic.h>
24 #include <dt-bindings/pinctrl/rzv2m-pinctrl.h>
30 #define DRV_NAME "pinctrl-rzv2m"
56 * n indicates number of pins in the port, a is the register index
114 struct pinctrl_pin_desc *pins; member
116 const struct rzv2m_pinctrl_data *data; member
144 rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 1); in rzv2m_pinctrl_set_pfc_mode()
145 rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 1); in rzv2m_pinctrl_set_pfc_mode()
148 addr = pctrl->base + PFSEL(port) + (pin / 4) * 4; in rzv2m_pinctrl_set_pfc_mode()
[all …]
Dpinctrl-rza2.c1 // SPDX-License-Identifier: GPL-2.0
23 #define DRIVER_NAME "pinctrl-rza2"
44 struct pinctrl_pin_desc *pins; member
51 #define RZA2_PDR(port) (0x0000 + (port) * 2) /* Direction 16-bit */
52 #define RZA2_PODR(port) (0x0040 + (port)) /* Output Data 8-bit */
53 #define RZA2_PIDR(port) (0x0060 + (port)) /* Input Data 8-bit */
54 #define RZA2_PMR(port) (0x0080 + (port)) /* Mode 8-bit */
55 #define RZA2_DSCR(port) (0x0140 + (port) * 2) /* Drive 16-bit */
56 #define RZA2_PFS(port, pin) (0x0200 + ((port) * 8) + (pin)) /* Fnct 8-bit */
58 #define RZA2_PWPR 0x02ff /* Write Protect 8-bit */
[all …]
/Linux-v6.1/drivers/pinctrl/vt8500/
Dpinctrl-wmt.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-wmt.h"
26 static inline void wmt_setbits(struct wmt_pinctrl_data *data, u32 reg, in wmt_setbits() argument
31 val = readl_relaxed(data->base + reg); in wmt_setbits()
33 writel_relaxed(val, data->base + reg); in wmt_setbits()
36 static inline void wmt_clearbits(struct wmt_pinctrl_data *data, u32 reg, in wmt_clearbits() argument
41 val = readl_relaxed(data->base + reg); in wmt_clearbits()
43 writel_relaxed(val, data->base + reg); in wmt_clearbits()
75 struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev); in wmt_pmx_get_function_groups() local
[all …]
/Linux-v6.1/sound/soc/
Dsoc-jack.c1 // SPDX-License-Identifier: GPL-2.0+
3 // soc-jack.c -- ALSA SoC jack handling
21 * snd_soc_jack_report - Report the current status for a jack
28 * DAPM pins will be enabled or disabled as appropriate and DAPM
44 dapm = &jack->card->dapm; in snd_soc_jack_report()
46 mutex_lock(&jack->mutex); in snd_soc_jack_report()
48 jack->status &= ~mask; in snd_soc_jack_report()
49 jack->status |= status & mask; in snd_soc_jack_report()
53 list_for_each_entry(pin, &jack->pins, list) { in snd_soc_jack_report()
54 int enable = pin->mask & jack->status; in snd_soc_jack_report()
[all …]
/Linux-v6.1/drivers/pinctrl/
Dpinctrl-lantiq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/pinctrl/pinctrl-lantiq.c
4 * based on linux/drivers/pinctrl/pinctrl-pxa3xx.c
16 #include "pinctrl-lantiq.h"
21 return info->num_grps; in ltq_get_group_count()
28 if (selector >= info->num_grps) in ltq_get_group_name()
30 return info->grps[selector].name; in ltq_get_group_name()
35 const unsigned **pins, in ltq_get_group_pins() argument
39 if (selector >= info->num_grps) in ltq_get_group_pins()
40 return -EINVAL; in ltq_get_group_pins()
[all …]
Dpinctrl-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <linux/firmware/xlnx-zynqmp.h>
20 #include <linux/pinctrl/pinconf-generic.h>
23 #include "pinctrl-utils.h"
44 * struct zynqmp_pmux_function - a pinmux function
60 * struct zynqmp_pinctrl - driver data
67 * This struct is stored as driver data and used to retrieve
69 * group pins.
80 * struct zynqmp_pctrl_group - Pin control group info
[all …]
Dpinctrl-single.c29 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/platform_data/pinctrl-single.h>
38 #define DRIVER_NAME "pinctrl-single"
42 * struct pcs_func_vals - mux function register offset and value pair
54 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
71 * struct pcs_conf_type - pinconf property name, pinconf param pair
81 * struct pcs_function - pinctrl function
103 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
104 * @offset: offset base of pins
105 * @npins: number pins with the same mux value of gpio function
[all …]
/Linux-v6.1/Documentation/driver-api/media/drivers/
Dbttv-devel.rst1 .. SPDX-License-Identifier: GPL-2.0
7 -------------------------
15 bttv-cards.c, which holds the information required for each board.
24 example. The file Documentation/admin-guide/media/bttv-cardlist.rst has a list
48 Below is a do-it-yourself description for you.
50 The bt8xx chips have 32 general purpose pins, and registers to control
51 these pins. One register is the output enable register
52 (``BT848_GPIO_OUT_EN``), it says which pins are actively driven by the
53 bt848 chip. Another one is the data register (``BT848_GPIO_DATA``), where
54 you can get/set the status if these pins. They can be used for input
[all …]
/Linux-v6.1/drivers/pinctrl/freescale/
Dpinctrl-imx1-core.c1 // SPDX-License-Identifier: GPL-2.0+
8 // Based on pinctrl-imx.c:
26 #include "pinctrl-imx1.h"
62 * IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX
64 * configuration A, input configuration B, GPIO in use and data direction.
67 * bit position and pin id. If they are represented by 2 bit, the lower 16 pins
68 * are in the first register and the upper 16 pins in the second (next)
78 return ipctl->base + port * MX1_PORT_STRIDE; in imx1_mem()
98 dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n", in imx1_write_2bit()
101 /* Get current state of pins */ in imx1_write_2bit()
[all …]

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