Home
last modified time | relevance | path

Searched +full:cs +full:- +full:out (Results 1 – 25 of 773) sorted by relevance

12345678910>>...31

/Linux-v5.15/drivers/gpu/drm/i915/gt/
Dintel_migrate.c1 // SPDX-License-Identifier: MIT
31 GEM_BUG_ON(engine->class != COPY_ENGINE_CLASS); in engine_supports_migration()
42 vm->insert_page(vm, px_dma(pt), d->offset, I915_CACHE_NONE, in insert_pte()
43 d->is_lmem ? PTE_LM : 0); in insert_pte()
44 d->offset += PAGE_SIZE; in insert_pte()
57 * to pre-allocate the page directories for the migration VM, this in migrate_vm()
66 * We lay the ppGTT out as: in migrate_vm()
68 * [0, CHUNK_SZ) -> first object in migrate_vm()
69 * [CHUNK_SZ, 2 * CHUNK_SZ) -> second object in migrate_vm()
70 * [2 * CHUNK_SZ, 2 * CHUNK_SZ + 2 * CHUNK_SZ >> 9] -> PTE in migrate_vm()
[all …]
Dselftest_engine_cs.c1 // SPDX-License-Identifier: GPL-2.0
21 return *a - *b; in cmp_u32()
29 atomic_inc(&gt->rps.num_waiters); in perf_begin()
30 schedule_work(&gt->rps.work); in perf_begin()
31 flush_work(&gt->rps.work); in perf_begin()
36 atomic_dec(&gt->rps.num_waiters); in perf_end()
39 return igt_flush_test(gt->i915); in perf_end()
45 rcu_dereference_protected(rq->timeline, in write_timestamp()
48 u32 *cs; in write_timestamp() local
50 cs = intel_ring_begin(rq, 4); in write_timestamp()
[all …]
Dselftest_execlists.c1 // SPDX-License-Identifier: MIT
23 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
46 tasklet_hi_schedule(&engine->sched_engine->tasklet); in wait_for_submit()
57 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit()
61 return -ETIME; in wait_for_submit()
77 if (READ_ONCE(engine->execlists.pending[0])) in wait_for_reset()
83 if (READ_ONCE(rq->fence.error)) in wait_for_reset()
89 if (rq->fence.error != -EIO) { in wait_for_reset()
91 engine->name, in wait_for_reset()
92 rq->fence.context, in wait_for_reset()
[all …]
Dselftest_timeline.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2017-2018 Intel Corporation
27 struct drm_i915_gem_object *obj = tl->hwsp_ggtt->obj; in hwsp_page()
30 return sg_page(obj->mm.pages->sgl); in hwsp_page()
37 return (address + offset_in_page(tl->hwsp_offset)) / TIMELINE_SEQNO_BYTES; in hwsp_cacheline()
47 err = i915_gem_object_lock(tl->hwsp_ggtt->obj, &ww); in selftest_tl_pin()
51 if (err == -EDEADLK) { in selftest_tl_pin()
79 tl = xchg(&state->history[idx], tl); in __mock_hwsp_record()
81 radix_tree_delete(&state->cachelines, hwsp_cacheline(tl)); in __mock_hwsp_record()
94 while (count--) { in __mock_hwsp_timeline()
[all …]
Dselftest_ring_submission.c1 // SPDX-License-Identifier: MIT
13 u32 *cs; in create_wally() local
16 obj = i915_gem_object_create_internal(engine->i915, 4096); in create_wally()
20 vma = i915_vma_instance(obj, engine->gt->vm, NULL); in create_wally()
38 cs = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC); in create_wally()
39 if (IS_ERR(cs)) { in create_wally()
41 return ERR_CAST(cs); in create_wally()
44 if (GRAPHICS_VER(engine->i915) >= 6) { in create_wally()
45 *cs++ = MI_STORE_DWORD_IMM_GEN4; in create_wally()
46 *cs++ = 0; in create_wally()
[all …]
Dselftest_rc6.c1 // SPDX-License-Identifier: MIT
34 struct intel_rc6 *rc6 = &gt->rc6; in live_rc6_manual()
47 if (!rc6->enabled) in live_rc6_manual()
51 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) in live_rc6_manual()
54 has_power = librapl_supported(gt->i915); in live_rc6_manual()
55 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in live_rc6_manual()
66 rc0_power = librapl_energy_uJ() - rc0_power; in live_rc6_manual()
69 if ((res[1] - res[0]) >> 10) { in live_rc6_manual()
71 (res[1] - res[0]) >> 10); in live_rc6_manual()
72 err = -EINVAL; in live_rc6_manual()
[all …]
Dselftest_workarounds.c1 // SPDX-License-Identifier: MIT
41 err = -EIO; in request_add_sync()
54 err = -ETIMEDOUT; in request_add_spin()
68 wa_init_start(&lists->gt_wa_list, "GT_REF", "global"); in reference_lists_init()
69 gt_init_workarounds(gt->i915, &lists->gt_wa_list); in reference_lists_init()
70 wa_init_finish(&lists->gt_wa_list); in reference_lists_init()
73 struct i915_wa_list *wal = &lists->engine[id].wa_list; in reference_lists_init()
75 wa_init_start(wal, "REF", engine->name); in reference_lists_init()
80 &lists->engine[id].ctx_wa_list, in reference_lists_init()
92 intel_wa_list_free(&lists->engine[id].wa_list); in reference_lists_fini()
[all …]
Dintel_ring_submission.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2008-2021 Intel Corporation
22 * set-context and then emitting the batch.
32 if (engine->class == RENDER_CLASS) { in set_hwstam()
33 if (GRAPHICS_VER(engine->i915) >= 6) in set_hwstam()
47 if (GRAPHICS_VER(engine->i915) >= 4) in set_hws_pga()
50 intel_uncore_write(engine->uncore, HWS_PGA, addr); in set_hws_pga()
55 struct drm_i915_gem_object *obj = engine->status_page.vma->obj; in status_page()
58 return sg_page(obj->mm.pages->sgl); in status_page()
75 if (GRAPHICS_VER(engine->i915) == 7) { in set_hwsp()
[all …]
/Linux-v5.15/drivers/misc/habanalabs/common/
Dcommand_submission.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
18 * enum hl_cs_wait_status - cs wait status
19 * @CS_WAIT_STATUS_BUSY: cs was not completed yet
20 * @CS_WAIT_STATUS_COMPLETED: cs completed
21 * @CS_WAIT_STATUS_GONE: cs completed but fence is already gone
39 struct hl_device *hdev = hw_sob->hdev; in hl_sob_reset()
41 dev_dbg(hdev->dev, "reset sob id %u\n", hw_sob->sob_id); in hl_sob_reset()
43 hdev->asic_funcs->reset_sob(hdev, hw_sob); in hl_sob_reset()
45 hw_sob->need_reset = false; in hl_sob_reset()
[all …]
Dhw_queue.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
13 * hl_queue_add_ptr - add to pi or ci and checks if it wraps around
23 ptr &= ((HL_QUEUE_LENGTH << 1) - 1); in hl_hw_queue_add_ptr()
28 return atomic_read(ci) & ((queue_len << 1) - 1); in queue_ci_get()
33 int delta = (q->pi - queue_ci_get(&q->ci, queue_len)); in queue_free_slots()
36 return (queue_len - delta); in queue_free_slots()
38 return (abs(delta) - queue_len); in queue_free_slots()
41 void hl_hw_queue_update_ci(struct hl_cs *cs) in hl_hw_queue_update_ci() argument
43 struct hl_device *hdev = cs->ctx->hdev; in hl_hw_queue_update_ci()
[all …]
/Linux-v5.15/drivers/gpu/drm/i915/selftests/
Di915_perf.c2 * SPDX-License-Identifier: MIT
17 #define TEST_OA_CONFIG_UUID "12345678-1234-1234-1234-1234567890ab"
26 return -ENOMEM; in alloc_empty_config()
28 oa_config->perf = perf; in alloc_empty_config()
29 kref_init(&oa_config->ref); in alloc_empty_config()
31 strlcpy(oa_config->uuid, TEST_OA_CONFIG_UUID, sizeof(oa_config->uuid)); in alloc_empty_config()
33 mutex_lock(&perf->metrics_lock); in alloc_empty_config()
35 oa_config->id = idr_alloc(&perf->metrics_idr, oa_config, 2, 0, GFP_KERNEL); in alloc_empty_config()
36 if (oa_config->id < 0) { in alloc_empty_config()
37 mutex_unlock(&perf->metrics_lock); in alloc_empty_config()
[all …]
Di915_request.c20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
74 request = mock_request(rcs0(i915)->kernel_context, HZ / 10); in igt_add_request()
76 return -ENOMEM; in igt_add_request()
88 int err = -EINVAL; in igt_wait_request()
92 request = mock_request(rcs0(i915)->kernel_context, T); in igt_wait_request()
94 return -ENOMEM; in igt_wait_request()
98 if (i915_request_wait(request, 0, 0) != -ETIME) { in igt_wait_request()
103 if (i915_request_wait(request, 0, T) != -ETIME) { in igt_wait_request()
115 if (i915_request_wait(request, 0, 0) != -ETIME) { in igt_wait_request()
125 if (i915_request_wait(request, 0, T / 2) != -ETIME) { in igt_wait_request()
[all …]
/Linux-v5.15/fs/fuse/
Ddev.c3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
37 * Lockless access is OK, because file->private data is set in fuse_get_dev()
40 return READ_ONCE(file->private_data); in fuse_get_dev()
45 INIT_LIST_HEAD(&req->list); in fuse_request_init()
46 INIT_LIST_HEAD(&req->intr_entry); in fuse_request_init()
47 init_waitqueue_head(&req->waitq); in fuse_request_init()
48 refcount_set(&req->count, 1); in fuse_request_init()
49 __set_bit(FR_PENDING, &req->flags); in fuse_request_init()
50 req->fm = fm; in fuse_request_init()
69 refcount_inc(&req->count); in __fuse_get_request()
[all …]
/Linux-v5.15/drivers/spi/
Dspi-omap2-mcspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/dma-mapping.h>
30 #include <linux/platform_data/spi-omap2-mcspi.h>
47 /* per-channel banks, 0x14 bytes each, first is: */
54 /* per-register bitmasks: */
90 /* We have 2 DMA channels per CS, one for RX and one for TX */
115 struct list_head cs; member
149 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
156 return readl_relaxed(mcspi->base + idx); in mcspi_read_reg()
162 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_cs_reg() local
[all …]
Dspi-fsl-espi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
39 /* eSPI Controller CS mode register definitions */
118 return ioread32be(espi->reg_base + offset); in fsl_espi_read_reg()
123 return ioread16be(espi->reg_base + offset); in fsl_espi_read_reg16()
128 return ioread8(espi->reg_base + offset); in fsl_espi_read_reg8()
134 iowrite32be(val, espi->reg_base + offset); in fsl_espi_write_reg()
140 iowrite16be(val, espi->reg_base + offset); in fsl_espi_write_reg16()
146 iowrite8(val, espi->reg_base + offset); in fsl_espi_write_reg8()
151 struct fsl_espi *espi = spi_master_get_devdata(m->spi->master); in fsl_espi_check_message()
154 if (m->frame_length > SPCOM_TRANLEN_MAX) { in fsl_espi_check_message()
[all …]
Dspi-dw-mmio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Memory-mapped interface driver for DW SPI Core
24 #include "spi-dw.h"
65 struct dw_spi *dws = spi_master_get_devdata(spi->master); in dw_spi_mscc_set_cs()
67 struct dw_spi_mscc *dwsmscc = dwsmmio->priv; in dw_spi_mscc_set_cs()
68 u32 cs = spi->chip_select; in dw_spi_mscc_set_cs() local
70 if (cs < 4) { in dw_spi_mscc_set_cs()
74 sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs)); in dw_spi_mscc_set_cs()
76 writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE); in dw_spi_mscc_set_cs()
88 dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL); in dw_spi_mscc_init()
[all …]
/Linux-v5.15/kernel/cgroup/
Dcpuset.c7 * Copyright (C) 2004-2007 Silicon Graphics, Inc.
11 * sysfs is Copyright (c) 2001-3 Patrick Mochel
13 * 2003-10-10 Written by Simon Derr.
14 * 2003-10-22 Updates by Stephen Hemminger.
15 * 2004 May-July Rework by Paul Jackson.
59 #include <linux/backing-dev.h>
89 * The user-configured masks can only be changed by writing to
103 * The user-configured masks are always the same with effective masks.
106 /* user-configured CPUs and Memory Nodes allow to tasks */
115 * CPUs allocated to child sub-partitions (default hierarchy only)
[all …]
/Linux-v5.15/drivers/gpu/drm/i915/gvt/
Dmmio_context.c2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
165 struct intel_gvt *gvt = engine->i915->gvt; in load_render_mocs()
166 struct intel_uncore *uncore = engine->uncore; in load_render_mocs()
167 u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt; in load_render_mocs()
168 u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list; in load_render_mocs()
177 if (!HAS_ENGINE(engine->gt, ring_id)) in load_render_mocs()
201 u32 *cs; in restore_context_mmio_for_inhibit() local
204 struct intel_gvt *gvt = vgpu->gvt; in restore_context_mmio_for_inhibit()
205 int ring_id = req->engine->id; in restore_context_mmio_for_inhibit()
[all …]
/Linux-v5.15/drivers/gpu/drm/i915/gem/selftests/
Di915_gem_coherency.c2 * SPDX-License-Identifier: MIT
31 i915_gem_object_lock(ctx->obj, NULL); in cpu_set()
32 err = i915_gem_object_prepare_write(ctx->obj, &needs_clflush); in cpu_set()
34 goto out; in cpu_set()
36 page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); in cpu_set()
49 i915_gem_object_finish_access(ctx->obj); in cpu_set()
51 out: in cpu_set()
52 i915_gem_object_unlock(ctx->obj); in cpu_set()
64 i915_gem_object_lock(ctx->obj, NULL); in cpu_get()
65 err = i915_gem_object_prepare_read(ctx->obj, &needs_clflush); in cpu_get()
[all …]
Di915_gem_client_blt.c1 // SPDX-License-Identifier: MIT
44 const int ver = GRAPHICS_VER(to_i915(batch->base.dev)); in prepare_blit()
47 u32 cmd, *cs; in prepare_blit() local
49 cs = i915_gem_object_pin_map_unlocked(batch, I915_MAP_WC); in prepare_blit()
50 if (IS_ERR(cs)) in prepare_blit()
51 return PTR_ERR(cs); in prepare_blit()
53 *cs++ = MI_LOAD_REGISTER_IMM(1); in prepare_blit()
54 *cs++ = i915_mmio_reg_offset(BCS_SWCTRL); in prepare_blit()
56 if (src->tiling == I915_TILING_Y) in prepare_blit()
58 if (dst->tiling == I915_TILING_Y) in prepare_blit()
[all …]
/Linux-v5.15/arch/arm64/boot/dts/hisilicon/
Dhi6220-coresight.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
14 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
17 clock-names = "apb_pclk";
19 out-ports {
22 remote-endpoint =
28 in-ports {
31 remote-endpoint =
39 compatible = "arm,coresight-tmc", "arm,primecell";
42 clock-names = "apb_pclk";
44 in-ports {
[all …]
/Linux-v5.15/arch/mips/include/asm/netlogic/xlr/
Dflash.h2 * Copyright (c) 2003-2012 Broadcom Corporation
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
37 #define FLASH_CSBASE_ADDR(cs) (cs) argument
38 #define FLASH_CSADDR_MASK(cs) (0x10 + (cs)) argument
39 #define FLASH_CSDEV_PARM(cs) (0x20 + (cs)) argument
40 #define FLASH_CSTIME_PARMA(cs) (0x30 + (cs)) argument
41 #define FLASH_CSTIME_PARMB(cs) (0x40 + (cs)) argument
48 #define FLASH_NAND_CLE(cs) (0x90 + (cs)) argument
49 #define FLASH_NAND_ALE(cs) (0xa0 + (cs)) argument
/Linux-v5.15/include/uapi/misc/
Dhabanalabs.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
3 * Copyright 2016-2020 HabanaLabs, Ltd.
15 * Defines that are asic-specific but constitutes as ABI between kernel driver
294 * HW_IP_INFO - Receive information about different IP blocks in the
296 * HL_INFO_HW_EVENTS - Receive an array describing how many times each event
298 * HL_INFO_DRAM_USAGE - Retrieve the dram usage inside the device and of the
301 * HL_INFO_HW_IDLE - Retrieve information about the idle status of each
303 * HL_INFO_DEVICE_STATUS - Retrieve the device's status. This opcode doesn't
305 * HL_INFO_DEVICE_UTILIZATION - Retrieve the total utilization of the device
310 * HL_INFO_HW_EVENTS_AGGREGATE - Receive an array describing how many times each
[all …]
/Linux-v5.15/tools/perf/util/
Ddata-convert-bt.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <babeltrace/ctf-writer/writer.h>
15 #include <babeltrace/ctf-writer/clock.h>
16 #include <babeltrace/ctf-writer/stream.h>
17 #include <babeltrace/ctf-writer/event.h>
18 #include <babeltrace/ctf-writer/event-types.h>
19 #include <babeltrace/ctf-writer/event-fields.h>
20 #include <babeltrace/ctf-ir/utils.h>
22 #include <traceevent/event-parse.h>
24 #include "data-convert.h"
[all …]
/Linux-v5.15/drivers/mtd/nand/raw/
Dau1550nd.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <asm/mach-au1x00/au1000.h>
16 #include <asm/mach-au1x00/au1550nd.h>
23 int cs; member
33 * au_write_buf - write buffer to chip
48 writeb(p[i], ctx->base + MEM_STNAND_DATA); in au_write_buf()
54 * au_read_buf - read chip data into buffer
69 p[i] = readb(ctx->base + MEM_STNAND_DATA); in au_read_buf()
75 * au_write_buf16 - write buffer to chip
91 writew(p[i], ctx->base + MEM_STNAND_DATA); in au_write_buf16()
[all …]

12345678910>>...31