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/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dbrcm,iproc-clocks.yaml16 LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
20 reference clock of the onboard crystal.
60 most iProc PLLs, this is an onboard crystal with a fixed rate.
109 crystal N/A N/A N/A
111 armpll crystal N/A N/A
113 keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK
114 adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK
115 pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK
117 genpll crystal 0 BCM_CYGNUS_GENPLL
125 lcpll0 crystal 0 BCM_CYGNUS_LCPLL0
[all …]
Dvf610-clock.txt16 - sxosc (external crystal oscillator 32KHz, recommended)
17 - fxosc (external crystal oscillator 24MHz, recommended)
Drenesas,r9a06g032-sysctrl.yaml23 - description: External 40 MHz crystal
24 - description: Optional external 32.768 kHz crystal
Didt,versaclock5.yaml140 # Devices with builtin crystal + optional external input
147 # Devices without builtin crystal
158 /* 25MHz reference crystal */
Dsamsung,s5pv210-clock.yaml18 - "xxti" - external crystal oscillator connected to XXTI and XXTO pins of
20 - "xusbxti" - external crystal oscillator connected to XUSBXTI and XUSBXTO
Drockchip,rk3188-cru.yaml25 - "xin24m" - crystal input - required
27 - "xin27m" - 27mhz crystal input on RK3066 - optional
/Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dpllnv04.c48 int crystal = info->refclk; in getMNP_single() local
55 /* possibly correlated with introduction of 27MHz crystal */ in getMNP_single()
93 if (crystal/M < minU) in getMNP_single()
95 if (crystal/M > maxU) in getMNP_single()
98 /* add crystal/2 to round better */ in getMNP_single()
99 N = (clkP * M + crystal/2) / crystal; in getMNP_single()
107 calcclk = ((N * crystal + P/2) / P + M/2) / M; in getMNP_single()
149 int crystal = info->refclk; in getMNP_double() local
165 if (crystal/M1 < minU1) in getMNP_double()
167 if (crystal/M1 > maxU1) in getMNP_double()
[all …]
/Linux-v6.1/arch/powerpc/boot/
Dmpc8xx.c19 /* Return system clock from crystal frequency */
20 u32 mpc885_get_clock(u32 crystal) in mpc885_get_clock() argument
46 ret = crystal * mfi; in mpc885_get_clock()
49 ret += crystal * mfn / (mfd + 1); in mpc885_get_clock()
70 int mpc885_fixup_clocks(u32 crystal) in mpc885_fixup_clocks() argument
72 u32 sysclk = mpc885_get_clock(crystal); in mpc885_fixup_clocks()
Dpq2.c25 /* Get various clocks from crystal frequency.
28 int pq2_get_clocks(u32 crystal, u32 *sysfreq, u32 *corefreq, in pq2_get_clocks() argument
50 mainclk = crystal * (pllmf + 1) / (plldf + 1); in pq2_get_clocks()
90 int pq2_fixup_clocks(u32 crystal) in pq2_fixup_clocks() argument
94 if (!pq2_get_clocks(crystal, &sysfreq, &corefreq, &timebase, &brgfreq)) in pq2_fixup_clocks()
Dmpc8xx.h9 u32 mpc885_get_clock(u32 crystal);
10 int mpc885_fixup_clocks(u32 crystal);
Dpq2.h7 int pq2_get_clocks(u32 crystal, u32 *sysfreq, u32 *corefreq,
10 int pq2_fixup_clocks(u32 crystal);
/Linux-v6.1/drivers/acpi/pmic/
Dintel_pmic_chtcrc.c3 * Intel Cherry Trail Crystal Cove PMIC operation region driver
16 * We have no docs for the CHT Crystal Cove PMIC. The Asus Zenfone-2 kernel
17 * code has 2 Crystal Cove regulator drivers, one calls the PMIC a "Crystal
24 * CHT Crystal Cove PMIC.
DKconfig14 bool "ACPI operation region support for Bay Trail Crystal Cove PMIC"
18 version of the Crystal Cove PMIC.
21 bool "ACPI operation region support for Cherry Trail Crystal Cove PMIC"
25 version of the Crystal Cove PMIC.
/Linux-v6.1/drivers/tty/serial/
Dmax3100.c15 .crystal = 0,
116 int crystal; /* 1 if 3.6864Mhz crystal 0 for 1.8432 */ member
439 if (s->crystal) in max3100_set_termios()
445 param_new = 14 + s->crystal; in max3100_set_termios()
448 param_new = 13 + s->crystal; in max3100_set_termios()
451 param_new = 12 + s->crystal; in max3100_set_termios()
454 param_new = 11 + s->crystal; in max3100_set_termios()
457 param_new = 10 + s->crystal; in max3100_set_termios()
460 param_new = 9 + s->crystal; in max3100_set_termios()
463 param_new = 8 + s->crystal; in max3100_set_termios()
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/rtc/
Dstmp3xxx-rtc.txt11 - stmp,crystal-freq: override crystal frequency as determined from fuse bits.
13 "no crystal".
/Linux-v6.1/include/linux/
Dserial_max3100.h15 * @crystal: 1 for 3.6864 Mhz, 0 for 1.8432
26 * .crystal = 0,
43 int crystal; member
/Linux-v6.1/Documentation/devicetree/bindings/mips/cavium/
Ductl.txt20 either "crystal" or "external".
31 /* Either "crystal" or "external" */
32 refclk-type = "crystal";
/Linux-v6.1/drivers/rtc/
Drtc-stmp3xxx.c303 * This clock can be provided by an external 32k crystal. If that one is in stmp3xxx_rtc_probe()
315 of_property_read_u32(pdev->dev.of_node, "stmp,crystal-freq", in stmp3xxx_rtc_probe()
320 /* keep 32kHz crystal running in low-power mode */ in stmp3xxx_rtc_probe()
327 /* keep 32.768kHz crystal running in low-power mode */ in stmp3xxx_rtc_probe()
335 "invalid crystal-freq specified in device-tree. Assuming no crystal\n"); in stmp3xxx_rtc_probe()
/Linux-v6.1/Documentation/devicetree/bindings/net/wireless/
Desp,esp8089.yaml19 esp,crystal-26M-en:
39 esp,crystal-26M-en = <2>;
/Linux-v6.1/Documentation/devicetree/bindings/usb/
Docteon-usb.txt25 "crystal" or "external".
54 cavium,refclk-type = "crystal";
/Linux-v6.1/arch/arm/mach-s3c/
Dinit.c69 * given master crystal value.
71 * xtal = 0 -> use default PLL crystal value (normally 12MHz)
72 * != 0 -> PLL crystal value in Hz
/Linux-v6.1/arch/x86/kernel/
Dtsc_msr.c24 * use a 25 MHz crystal and Cherry Trail uses a 19.2 MHz crystal, the crystal
138 * 24 MHz crystal? : 24 * 13 / 4 = 78 MHz
/Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
Dgf119.c114 return (device->crystal * 1000) / 20; in gf119_fan_pwm_clock()
116 return device->crystal * 1000 / 10; in gf119_fan_pwm_clock()
130 nvkm_wr32(device, 0x00e724, device->crystal * 1000); in gf119_therm_init()
/Linux-v6.1/Documentation/devicetree/bindings/sound/
Dcs43130.txt20 When external MCLK is generated by external crystal
22 for external crystal. Amount of bias current sent is
/Linux-v6.1/Documentation/input/devices/
Dcs461x.rst1 Crystal SoundFusion CS4610/CS4612/CS461 joystick
5 Crystal SoundFusion CS4610/CS4612/CS4615. This code is based upon

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