| /Linux-v5.15/Documentation/x86/ |
| D | topology.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 The architecture-agnostic topology definitions are in
12 Documentation/admin-guide/cputopology.rst. This file holds x86-specific
17 Needless to say, code should use the generic functions - this file is *only*
35 - packages
36 - cores
37 - threads
48 Package-related topology information in the kernel:
50 - cpuinfo_x86.x86_max_cores:
54 - cpuinfo_x86.x86_max_dies:
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| /Linux-v5.15/arch/mips/kernel/ |
| D | smp-cps.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/cpu.h>
18 #include <asm/mips-cps.h>
21 #include <asm/pm-cps.h>
23 #include <asm/smp-cps.h>
39 static unsigned core_vpe_count(unsigned int cluster, unsigned core) in core_vpe_count() argument
44 return mips_cps_numvps(cluster, core); in core_vpe_count()
70 /* Use the number of VPEs in cluster 0 core 0 for smp_num_siblings */ in cps_smp_setup()
74 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) { in cps_smp_setup()
87 /* Indicate present CPUs (CPU being synonymous with VPE) */ in cps_smp_setup()
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| /Linux-v5.15/Documentation/admin-guide/pm/ |
| D | intel-speed-select.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 collection of features that give more granular control over CPU performance.
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
38 # cd tools/power/x86/intel-speed-select/
43 ------------
47 # intel-speed-select --help
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| /Linux-v5.15/Documentation/devicetree/bindings/cpu/ |
| D | cpu-topology.txt | 2 CPU topology binding description
6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
17 The bottom hierarchy level sits at core or thread level depending on whether
18 symmetric multi-threading (SMT) is supported or not.
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
22 In systems where SMT is not supported "cpu" nodes represent all cores present
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| /Linux-v5.15/arch/powerpc/include/asm/ |
| D | cputhreads.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
13 * threads per core and the same number for each core in the system
15 * as the CPU numbers are still allocated, just not brought online).
35 /* cpu_thread_mask_to_cores - Return a cpumask of one per cores
40 * This function returns a cpumask which will have one online cpu's
41 * bit set for each core that has at least one thread set in the argument.
44 * since those need to be done only once per core/TLB
49 int i, cpu; in cpu_thread_mask_to_cores() local
55 cpu = cpumask_next_and(-1, &tmp, cpu_online_mask); in cpu_thread_mask_to_cores()
56 if (cpu < nr_cpu_ids) in cpu_thread_mask_to_cores()
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| /Linux-v5.15/tools/perf/util/ |
| D | bpf_counter_cgroup.c | 1 // SPDX-License-Identifier: GPL-2.0
42 #define FD(evt, cpu) (*(int *)xyarray__entry(evt->core.fd, cpu, 0)) argument
49 __u32 i, cpu; in bperf_load_program() local
50 __u32 nr_cpus = evlist->core.all_cpus->nr; in bperf_load_program()
58 return -1; in bperf_load_program()
61 skel->rodata->num_cpus = total_cpus; in bperf_load_program()
62 skel->rodata->num_events = evlist->core.nr_entries / nr_cgroups; in bperf_load_program()
64 BUG_ON(evlist->core.nr_entries % nr_cgroups != 0); in bperf_load_program()
66 /* we need one copy of events per cpu for reading */ in bperf_load_program()
67 map_size = total_cpus * evlist->core.nr_entries / nr_cgroups; in bperf_load_program()
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| D | evsel.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Parts came from builtin-{top,stat,record}.c, see those files for further
15 #include <traceevent/event-parse.h>
44 #include "trace-event.h"
50 #include "pmu-hybrid.h"
51 #include "../perf-sys.h"
52 #include "util/parse-branch-options.h"
91 return -EINVAL; in evsel__object_config()
105 #define FD(e, x, y) (*(int *)xyarray__entry(e->core.fd, x, y))
124 * __perf_evsel__calc_id_pos - calculate id_pos.
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| D | evsel.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
33 /** struct evsel - event selector
35 * @evlist - evlist this evsel is in, if it is in one.
36 * @core - libperf evsel object
37 * @name - Can be set to retain the original event name passed by the user,
44 * PERF_SAMPLE_IDENTIFIER) in a non-sample event i.e. if sample_id_all
45 * is used there is an id sample appended to non-sample events
49 struct perf_evsel core; member
57 * These fields can be set in the parse-events code or similar.
138 * 1. perf-stat -b counting events used byBPF programs
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| D | mmap.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-2017, Red Hat Inc, Arnaldo Carvalho de Melo <acme@redhat.com>
5 * Parts came from evlist.c builtin-{top,stat,record}.c, see those files for further
34 len = bitmap_scnprintf(mask->bits, mask->nbits, buf, MASK_SIZE); in mmap_cpu_mask__scnprintf()
36 pr_debug("%p: %s mask[%zd]: %s\n", mask, tag, mask->nbits, buf); in mmap_cpu_mask__scnprintf()
41 return perf_mmap__mmap_len(&map->core); in mmap__mmap_len()
73 return map->aio.nr_cblocks > 0; in perf_mmap__aio_enabled()
79 map->aio.data[idx] = mmap(NULL, mmap__mmap_len(map), PROT_READ|PROT_WRITE, in perf_mmap__aio_alloc()
81 if (map->aio.data[idx] == MAP_FAILED) { in perf_mmap__aio_alloc()
82 map->aio.data[idx] = NULL; in perf_mmap__aio_alloc()
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| /Linux-v5.15/arch/arm/mach-bcm/ |
| D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014-2015 Broadcom Corporation
12 #include <linux/irqchip/irq-bcm2836.h>
34 #define OF_SECONDARY_BOOT "secondary-boot-reg"
54 return -ENXIO; in scu_a9_enable()
60 pr_err("hardware reports only one core\n"); in scu_a9_enable()
61 return -ENOENT; in scu_a9_enable()
68 return -ENOMEM; in scu_a9_enable()
78 static u32 secondary_boot_addr_for(unsigned int cpu) in secondary_boot_addr_for() argument
81 struct device_node *cpu_node = of_get_cpu_node(cpu, NULL); in secondary_boot_addr_for()
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| /Linux-v5.15/tools/power/cpupower/lib/ |
| D | cpupower.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) 2004-2009 Dominik Brodowski <linux@dominikbrodowski.de>
23 if (fd == -1) in cpupower_read_sysfs()
26 numread = read(fd, buf, buflen - 1); in cpupower_read_sysfs()
44 if (fd == -1) in cpupower_write_sysfs()
47 numwritten = write(fd, buf, buflen - 1); in cpupower_write_sysfs()
51 return -1; in cpupower_write_sysfs()
60 * Detect whether a CPU is online
63 * 1 -> if CPU is online
64 * 0 -> if CPU is offline
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| /Linux-v5.15/Documentation/devicetree/bindings/regulator/ |
| D | nvidia,tegra-regulators-coupling.txt | 4 NVIDIA Tegra SoC's have a mandatory voltage-coupling between regulators.
9 ------------------------
11 On Tegra20 SoC's there are 3 coupled regulators: CORE, RTC and CPU.
12 The CORE and RTC voltages shall be in a range of 170mV from each other
13 and they both shall be higher than the CPU voltage by at least 120mV.
16 ------------------------
18 On Tegra30 SoC's there are 2 coupled regulators: CORE and CPU. The CORE
19 and CPU voltages shall be in a range of 300mV from each other and CORE
20 voltage shall be higher than the CPU by N mV, where N depends on the CPU
24 - nvidia,tegra-core-regulator: Boolean property that designates regulator
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| /Linux-v5.15/tools/perf/tests/ |
| D | topology.c | 1 // SPDX-License-Identifier: GPL-2.0
14 #define TEMPL "/tmp/perf-test-XXXXXX"
26 return -1; in get_temp()
45 session->evlist = evlist__new_default(); in session_write_header()
46 TEST_ASSERT_VAL("can't get evlist", session->evlist); in session_write_header()
50 session->evlist = evlist__new(); in session_write_header()
51 TEST_ASSERT_VAL("can't get evlist", session->evlist); in session_write_header()
52 parse_events(session->evlist, "cpu_core/cycles/", &err); in session_write_header()
55 perf_header__set_feat(&session->header, HEADER_CPU_TOPOLOGY); in session_write_header()
56 perf_header__set_feat(&session->header, HEADER_NRCPUS); in session_write_header()
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| /Linux-v5.15/arch/mips/loongson64/ |
| D | smp.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/cpu.h>
54 static u32 (*ipi_read_clear)(int cpu);
55 static void (*ipi_write_action)(int cpu, u32 action);
56 static void (*ipi_write_enable)(int cpu);
57 static void (*ipi_clear_buf)(int cpu);
58 static void (*ipi_write_buf)(int cpu, struct task_struct *idle);
60 /* send mail via Mail_Send register for 3A4000+ CPU */
61 static void csr_mail_send(uint64_t data, int cpu, int mailbox) in csr_mail_send() argument
68 val |= (cpu << CSR_MAIL_SEND_CPU_SHIFT); in csr_mail_send()
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| /Linux-v5.15/Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,idle-state.txt | 3 ARM provides idle-state node to define the cpuidle states, as defined in [1].
4 cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
6 The idle states supported by the QCOM SoC are defined as -
14 When the WFI instruction is executed the ARM core would gate its internal
17 interrupt to trigger the core back in to active. This triggers the cache
20 cache hierarchy is also out of standby, and then the cpu is allowed to resume
26 Retention: Retention is a low power state where the core is clock gated and
27 the memory and the registers associated with the core are retained. The
30 sequence and would wait for interrupt, before restoring the cpu to execution
33 Standalone PC: A cpu can power down and warmboot if there is a sufficient time
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| /Linux-v5.15/arch/mips/netlogic/xlp/ |
| D | wakeup.c | 2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
39 #include <asm/asm-offsets.h>
46 #include <asm/netlogic/mips-extns.h>
48 #include <asm/netlogic/xlp-hal/iomap.h>
49 #include <asm/netlogic/xlp-hal/xlp.h>
50 #include <asm/netlogic/xlp-hal/pic.h>
51 #include <asm/netlogic/xlp-hal/sys.h>
53 static int xlp_wakeup_core(uint64_t sysbase, int node, int core) in xlp_wakeup_core() argument
58 coremask = (1 << core); in xlp_wakeup_core()
60 /* Enable CPU clock in case of 8xx/3xx */ in xlp_wakeup_core()
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| /Linux-v5.15/drivers/cpuidle/ |
| D | cpuidle-cps.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <asm/pm-cps.h>
17 STATE_NC_WAIT, /* MIPS wait instruction, non-coherent */
18 STATE_CLOCK_GATED, /* Core clock gated */
19 STATE_POWER_GATED, /* Core power gated */
30 * At least one core must remain powered up & clocked in order for the in cps_nc_enter()
33 * TODO: don't treat core 0 specially, just prevent the final core in cps_nc_enter()
36 if (cpus_are_siblings(0, dev->cpu) && (index > STATE_NC_WAIT)) in cps_nc_enter()
52 return -EINVAL; in cps_nc_enter()
55 /* Notify listeners the CPU is about to power down */ in cps_nc_enter()
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| /Linux-v5.15/drivers/watchdog/ |
| D | octeon-wdt-main.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2007-2017 Cavium, Inc.
11 * (c) Copyright 1996-1997 Alan Cox <alan@lxorguk.ukuu.org.uk>,
16 * "AS-IS" and at no charge.
39 * A watchdog is maintained for each CPU in the system, that way if
40 * one CPU suffers a lockup, we also get a register dump and reset.
55 #include <linux/cpu.h>
63 #include <asm/octeon/cvmx-boot-vector.h>
64 #include <asm/octeon/cvmx-ciu2-defs.h>
65 #include <asm/octeon/cvmx-rst-defs.h>
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| /Linux-v5.15/arch/powerpc/perf/ |
| D | imc-pmu.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * In-Memory Collection (IMC) Performance Monitor counter support.
12 #include <asm/imc-pmu.h>
20 * Used to avoid races in counting the nest-pmu units during hotplug
30 /* Core IMC data structures and variables */
49 * core and trace-imc
59 return container_of(event->pmu, struct imc_pmu, pmu); in imc_event_to_pmu()
62 PMU_FORMAT_ATTR(event, "config:0-61");
63 PMU_FORMAT_ATTR(offset, "config:0-31");
65 PMU_FORMAT_ATTR(mode, "config:33-40");
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| /Linux-v5.15/drivers/base/ |
| D | arch_topology.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Arch specific cpu topology information
10 #include <linux/cpu.h>
61 int cpu; in topology_set_scale_freq_source() local
72 for_each_cpu(cpu, cpus) { in topology_set_scale_freq_source()
73 sfd = rcu_dereference(*per_cpu_ptr(&sft_data, cpu)); in topology_set_scale_freq_source()
76 if (!sfd || sfd->source != SCALE_FREQ_SOURCE_ARCH) { in topology_set_scale_freq_source()
77 rcu_assign_pointer(per_cpu(sft_data, cpu), data); in topology_set_scale_freq_source()
78 cpumask_set_cpu(cpu, &scale_freq_counters_mask); in topology_set_scale_freq_source()
92 int cpu; in topology_clear_scale_freq_source() local
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| /Linux-v5.15/Documentation/devicetree/bindings/clock/ |
| D | mvebu-core-clock.txt | 1 * Core Clock bindings for Marvell MVEBU SoCs
3 Marvell MVEBU SoCs usually allow to determine core clock frequencies by
4 reading the Sample-At-Reset (SAR) register. The core clock consumer should
9 1 = cpuclk (CPU clock)
16 1 = cpuclk (CPU clock)
22 1 = cpuclk (CPU clock)
28 1 = cpuclk (CPU clock)
36 1 = cpuclk (CPU clock)
52 - compatible : shall be one of the following:
53 "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
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| /Linux-v5.15/drivers/edac/ |
| D | octeon_edac-pc.c | 9 * written by Ralf Baechle <ralf@linux-mips.org>
34 * EDAC CPU cache error callback
36 * @event: non-zero if unrecoverable.
44 unsigned int core = cvmx_get_core_num(); in co_cache_error_event() local
45 unsigned int cpu = smp_processor_id(); in co_cache_error_event() local
50 dcache_err = cache_err_dcache[core]; in co_cache_error_event()
51 cache_err_dcache[core] = 0; in co_cache_error_event()
57 edac_device_printk(p->ed, KERN_ERR, in co_cache_error_event()
58 "CacheErr (Icache):%llx, core %d/cpu %d, cp0_errorepc == %lx\n", in co_cache_error_event()
59 (unsigned long long)icache_err, core, cpu, in co_cache_error_event()
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| /Linux-v5.15/drivers/hwmon/ |
| D | coretemp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * coretemp.c - Linux kernel module for hardware monitoring
18 #include <linux/hwmon-sysfs.h>
23 #include <linux/cpu.h>
34 * force_tjmax only matters when TjMax can't be read from the CPU itself.
43 #define NUM_REAL_CORES 128 /* Number of Real cores per cpu */
49 #define TO_CORE_ID(cpu) (cpu_data(cpu).cpu_core_id) argument
50 #define TO_ATTR_NO(cpu) (TO_CORE_ID(cpu) + BASE_SYSFS_ATTR_NO) argument
53 #define for_each_sibling(i, cpu) \ argument
54 for_each_cpu(i, topology_sibling_cpumask(cpu))
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| /Linux-v5.15/Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra20-pmc.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra20-pmc
18 - nvidia,tegra30-pmc
19 - nvidia,tegra114-pmc
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| /Linux-v5.15/Documentation/arm/samsung-s3c24xx/ |
| D | cpufreq.rst | 6 ------------
9 the ability to change the core, memory and peripheral operating
10 frequencies. The core control is exported via the CPUFreq driver
12 rate the core is running at.
14 There are two forms of the driver depending on the specific CPU and
19 ARM core is available as a separate driver.
23 ------
25 The code core manages the CPU specific drivers, any data that they
27 system. Each CPU registers a driver to control the PLL, clock dividers
31 The core registers with drivers/cpufreq at init time if all the data
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