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/Linux-v6.1/arch/mips/kernel/
Dcevt-bcm1480.c1 // SPDX-License-Identifier: GPL-2.0-or-later
33 unsigned int cpu = smp_processor_id(); in sibyte_set_periodic() local
34 void __iomem *cfg, *init; in sibyte_set_periodic() local
36 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_set_periodic()
37 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); in sibyte_set_periodic()
39 __raw_writeq(0, cfg); in sibyte_set_periodic()
40 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init); in sibyte_set_periodic()
41 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg); in sibyte_set_periodic()
47 unsigned int cpu = smp_processor_id(); in sibyte_shutdown() local
48 void __iomem *cfg; in sibyte_shutdown() local
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Dcevt-sb1250.c1 // SPDX-License-Identifier: GPL-2.0-or-later
31 void __iomem *cfg; in sibyte_shutdown() local
33 cfg = IOADDR(A_SCD_TIMER_REGISTER(smp_processor_id(), R_SCD_TIMER_CFG)); in sibyte_shutdown()
36 __raw_writeq(0, cfg); in sibyte_shutdown()
43 unsigned int cpu = smp_processor_id(); in sibyte_set_periodic() local
44 void __iomem *cfg, *init; in sibyte_set_periodic() local
46 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_set_periodic()
47 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); in sibyte_set_periodic()
49 __raw_writeq(0, cfg); in sibyte_set_periodic()
50 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init); in sibyte_set_periodic()
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Dsmp-bmips.c20 #include <linux/cpu.h>
40 #include <asm/cpu-features.h>
53 static void bmips_set_reset_vec(int cpu, u32 val);
57 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
61 static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
62 static void bmips5000_send_ipi_single(int cpu, unsigned int action);
70 #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift)) argument
71 #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8)) argument
72 #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8)) argument
73 #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0)) argument
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/Linux-v6.1/arch/ia64/kernel/
Dirq_ia64.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 1998-2001 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
15 * Added CPU Hotplug handling for IPF.
58 static cpumask_t vector_allocation_domain(int cpu);
61 * Legacy IRQ to IA-64 vector translation table.
73 [0 ... NR_IRQS - 1] = {
80 [0 ... IA64_NUM_VECTORS - 1] = -1
84 [0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
88 [0 ... NR_IRQS -1] = IRQ_UNUSED
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Dmsi_ia64.c1 // SPDX-License-Identifier: GPL-2.0
21 int cpu = cpumask_first_and(cpu_mask, cpu_online_mask); in ia64_set_msi_irq_affinity() local
22 unsigned int irq = idata->irq; in ia64_set_msi_irq_affinity()
24 if (irq_prepare_move(irq, cpu)) in ia64_set_msi_irq_affinity()
25 return -1; in ia64_set_msi_irq_affinity()
31 addr |= MSI_ADDR_DEST_ID_CPU(cpu_physical_id(cpu)); in ia64_set_msi_irq_affinity()
40 irq_data_update_affinity(idata, cpumask_of(cpu)); in ia64_set_msi_irq_affinity()
87 irq_complete_move(data->irq); in ia64_ack_msi_irq()
94 unsigned int vector = irq_to_vector(data->irq); in ia64_msi_retrigger_irq()
104 .name = "PCI-MSI",
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/Linux-v6.1/drivers/cpufreq/
Ds3c24xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2006-2008 Simtec Electronics
7 * S3C24XX CPU Frequency scaling
17 #include <linux/cpu.h>
24 #include <linux/soc/samsung/s3c-cpufreq-core.h>
25 #include <linux/soc/samsung/s3c-pm.h>
58 static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg) in s3c_cpufreq_getcur() argument
62 cfg->freq.fclk = fclk = clk_get_rate(clk_fclk); in s3c_cpufreq_getcur()
63 cfg->freq.hclk = hclk = clk_get_rate(clk_hclk); in s3c_cpufreq_getcur()
64 cfg->freq.pclk = pclk = clk_get_rate(clk_pclk); in s3c_cpufreq_getcur()
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Ds3c2440-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2006-2009 Simtec Electronics
8 * S3C2440/S3C2442 CPU Frequency scaling
23 #include <linux/soc/samsung/s3c-cpufreq-core.h>
24 #include <linux/soc/samsung/s3c-pm.h>
54 long diff = a - b; in within_khz()
56 return (diff >= -1000 && diff <= 1000); in within_khz()
60 * s3c2440_cpufreq_calcdivs - calculate divider settings
61 * @cfg: The cpu frequency settings.
64 * specified in @cfg. The values are stored in @cfg for later use
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/Linux-v6.1/arch/x86/kernel/apic/
Dmsi.c1 // SPDX-License-Identifier: GPL-2.0-only
26 static void irq_msi_update_msg(struct irq_data *irqd, struct irq_cfg *cfg) in irq_msi_update_msg() argument
30 __irq_msi_compose_msg(cfg, msg, false); in irq_msi_update_msg()
31 irq_data_get_irq_chip(irqd)->irq_write_msi_msg(irqd, msg); in irq_msi_update_msg()
37 struct irq_cfg old_cfg, *cfg = irqd_cfg(irqd); in msi_set_affinity() local
38 struct irq_data *parent = irqd->parent_data; in msi_set_affinity()
39 unsigned int cpu; in msi_set_affinity() local
43 cpu = cpumask_first(irq_data_get_effective_affinity_mask(irqd)); in msi_set_affinity()
44 old_cfg = *cfg; in msi_set_affinity()
47 ret = parent->chip->irq_set_affinity(parent, mask, force); in msi_set_affinity()
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Dipi.c1 // SPDX-License-Identifier: GPL-2.0
33 * - Disabled on the command line in apic_smt_update()
34 * - Only a single CPU is online in apic_smt_update()
35 * - Not all present CPUs have been at least booted once in apic_smt_update()
55 apic->send_IPI_allbutself(vector); in apic_send_IPI_allbutself()
57 apic->send_IPI_mask_allbutself(cpu_online_mask, vector); in apic_send_IPI_allbutself()
61 * Send a 'reschedule' IPI to another CPU. It goes straight through and
65 void native_smp_send_reschedule(int cpu) in native_smp_send_reschedule() argument
67 if (unlikely(cpu_is_offline(cpu))) { in native_smp_send_reschedule()
68 WARN(1, "sched: Unexpected reschedule of offline CPU#%d!\n", cpu); in native_smp_send_reschedule()
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/Linux-v6.1/arch/arm/mach-omap2/
Domap-smp.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <linux/irqchip/arm-gic.h>
25 #include "omap-secure.h"
26 #include "omap-wakeupgen.h"
52 static struct omap_smp_config cfg; variable
71 return cfg.scu_base; in omap4_get_scu_base()
87 * BIT(27) - Disables streaming. All write-allocate lines allocate in in omap5_erratum_workaround_801819()
89 * BIT(25) - Disables streaming. All write-allocate lines allocate in in omap5_erratum_workaround_801819()
100 pr_debug("%s: ARM erratum workaround 801819 applied on CPU%d\n", in omap5_erratum_workaround_801819()
139 pr_debug("%s: ARM ACR setup for CVE_2017_5715 applied on CPU%d\n", in omap5_secondary_harden_predictor()
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/Linux-v6.1/arch/mips/loongson64/
Dhpet.c1 // SPDX-License-Identifier: GPL-2.0
35 unsigned int cfg = smbus_read(offset); in smbus_enable() local
37 cfg |= bit; in smbus_enable()
38 smbus_write(offset, cfg); in smbus_enable()
53 unsigned int cfg = hpet_read(HPET_CFG); in hpet_start_counter() local
55 cfg |= HPET_CFG_ENABLE; in hpet_start_counter()
56 hpet_write(HPET_CFG, cfg); in hpet_start_counter()
61 unsigned int cfg = hpet_read(HPET_CFG); in hpet_stop_counter() local
63 cfg &= ~HPET_CFG_ENABLE; in hpet_stop_counter()
64 hpet_write(HPET_CFG, cfg); in hpet_stop_counter()
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/Linux-v6.1/arch/x86/kernel/
Dhpet.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/cpu.h>
28 unsigned int cpu; member
133 * is_hpet_enabled - Check whether the legacy HPET timer interrupt is enabled
143 u32 i, id, period, cfg, status, channels, l, h; in _hpet_print_config() local
151 cfg = hpet_readl(HPET_CFG); in _hpet_print_config()
153 pr_info("CFG: 0x%x, STATUS: 0x%x\n", cfg, status); in _hpet_print_config()
210 hd.hd_irq[i] = hc->irq; in hpet_reserve_platform_timers()
212 switch (hc->mode) { in hpet_reserve_platform_timers()
215 hc->mode = HPET_MODE_DEVICE; in hpet_reserve_platform_timers()
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/Linux-v6.1/drivers/tty/
Dmips_ejtag_fdc.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2007-2015 Imagination Technologies Ltd
87 * struct mips_ejtag_fdc_tty_port - Wrapper struct for FDC tty_port.
117 * struct mips_ejtag_fdc_tty - Driver data for FDC as a whole.
120 * @cpu: CPU number for this FDC.
123 * @ports: Per-channel data.
144 unsigned int cpu; member
174 __raw_writel(data, priv->reg + offs); in mips_ejtag_fdc_write()
180 return __raw_readl(priv->reg + offs); in mips_ejtag_fdc_read()
186 * struct fdc_word - FDC word encoding some number of bytes of data.
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/Linux-v6.1/arch/arm/mach-s3c/
Dinit.c1 // SPDX-License-Identifier: GPL-2.0
7 // S3C series CPU initialisation
26 #include "cpu.h"
29 static struct cpu_table *cpu; variable
35 for (; count != 0; count--, tab++) { in s3c_lookup_cpu()
36 if ((idcode & tab->idmask) == (tab->idcode & tab->idmask)) in s3c_lookup_cpu()
46 cpu = s3c_lookup_cpu(idcode, cputab, cputab_size); in s3c_init_cpu()
48 if (cpu == NULL) { in s3c_init_cpu()
49 printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode); in s3c_init_cpu()
50 panic("Unknown S3C24XX CPU"); in s3c_init_cpu()
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/Linux-v6.1/tools/testing/selftests/bpf/map_tests/
Dtask_storage_map.c1 // SPDX-License-Identifier: GPL-2.0
33 while (!ctx->start) in lookup_fn()
36 while (!ctx->stop && i++ < ctx->loop) in lookup_fn()
37 bpf_map_lookup_elem(ctx->map_fd, &ctx->pid_fd, &value); in lookup_fn()
45 ctx->stop = true; in abort_lookup()
46 ctx->start = true; in abort_lookup()
54 unsigned int i, nr = 256, loop = 8192, cpu = 0; in test_task_storage_map_stress_lookup() local
59 const char *cfg; in test_task_storage_map_stress_lookup() local
62 cfg = getenv("TASK_STORAGE_MAP_NR_THREAD"); in test_task_storage_map_stress_lookup()
63 if (cfg) { in test_task_storage_map_stress_lookup()
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/Linux-v6.1/drivers/clk/samsung/
Dclk-cpu.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * This file contains the utility function to register CPU clock for Samsung
10 * Exynos platforms. A CPU clock is defined as a clock supplied to a CPU or a
11 * group of CPUs. The CPU clock is typically derived from a hierarchy of clock
13 * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
14 * clock for CPU domain. The rates of these auxiliary clocks are related to the
15 * CPU clock rate and this relation is usually specified in the hardware manual
18 * The below implementation of the CPU clock allows the rate changes of the CPU
19 * clock and the corresponding rate changes of the auxillary clocks of the CPU
22 * registers to acheive a fast co-oridinated rate change for all the CPU domain
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Dclk-cpu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 * struct exynos_cpuclk_data: config data to setup cpu clocks.
19 * This structure holds the divider configuration data for dividers in the CPU
22 * For CPU clock domains that do not have a DIV1 register, the @div1 member
32 * struct exynos_cpuclk: information about clock supplied to a CPU core.
33 * @hw: handle between CCF and CPU clock.
37 * @lock: cpu clock domain register access lock.
38 * @cfg: cpu clock rate configuration data.
39 * @num_cfgs: number of array elements in @cfg array.
42 * @flags: configuration flags for the CPU clock.
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/Linux-v6.1/arch/arm/mach-imx/
Dmmdc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
75 { .compatible = "fsl,imx6q-mmdc", .data = (void *)&imx6q_data},
76 { .compatible = "fsl,imx6qp-mmdc", .data = (void *)&imx6qp_data},
85 PMU_EVENT_ATTR_STRING(total-cycles, mmdc_pmu_total_cycles, "event=0x00")
86 PMU_EVENT_ATTR_STRING(busy-cycles, mmdc_pmu_busy_cycles, "event=0x01")
87 PMU_EVENT_ATTR_STRING(read-accesses, mmdc_pmu_read_accesses, "event=0x02")
88 PMU_EVENT_ATTR_STRING(write-accesses, mmdc_pmu_write_accesses, "event=0x03")
89 PMU_EVENT_ATTR_STRING(read-bytes, mmdc_pmu_read_bytes, "event=0x04")
90 PMU_EVENT_ATTR_STRING(read-bytes.unit, mmdc_pmu_read_bytes_unit, "MB");
91 PMU_EVENT_ATTR_STRING(read-bytes.scale, mmdc_pmu_read_bytes_scale, "0.000001");
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/Linux-v6.1/include/linux/soc/samsung/
Ds3c-cpufreq-core.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2006-2009 Simtec Electronics
7 * S3C CPU frequency scaling support - core support
12 #include <linux/soc/samsung/s3c-cpu-freq.h>
20 * struct s3c2410_iobank_timing - IO bank timings for S3C2410 style timings
31 * used by the CPU frequency support if it needs to change the settings
46 * struct s3c2412_iobank_timing - io timings for PL092 (S3C2412) style IO
86 * struct s3c_iotimings - Chip IO timings holder
94 * struct s3c_plltab - PLL table information.
104 * struct s3c_cpufreq_config - current cpu frequency configuration
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/Linux-v6.1/drivers/irqchip/
Dirq-ls-scfg-msi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Freescale SCFG MSI(-X) support
52 struct ls_scfg_msi_cfg *cfg; member
76 if (p && strncmp(p, "no-affinity", 11) == 0) in early_parse_ls_scfg_msi()
89 msg->address_hi = upper_32_bits(msi_data->msiir_addr); in ls_scfg_msi_compose_msg()
90 msg->address_lo = lower_32_bits(msi_data->msiir_addr); in ls_scfg_msi_compose_msg()
91 msg->data = data->hwirq; in ls_scfg_msi_compose_msg()
97 msg->data |= cpumask_first(mask); in ls_scfg_msi_compose_msg()
107 u32 cpu; in ls_scfg_msi_set_affinity() local
110 return -EINVAL; in ls_scfg_msi_set_affinity()
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/Linux-v6.1/arch/x86/events/intel/
Dcstate.c20 * This file export cstate related free running (read-only) counters
27 * The events only support system-wide mode counting. There is no
32 * - 'cstate_core': The counter is available for each physical core.
34 * - 'cstate_pkg': The counter is available for each physical package.
37 * All of these counters are specified in the Intel® 64 and IA-32
107 #include <asm/intel-family.h>
128 /* Model -> events mapping */
158 PMU_EVENT_ATTR_STRING(c1-residency, attr_cstate_core_c1, "event=0x00");
159 PMU_EVENT_ATTR_STRING(c3-residency, attr_cstate_core_c3, "event=0x01");
160 PMU_EVENT_ATTR_STRING(c6-residency, attr_cstate_core_c6, "event=0x02");
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/Linux-v6.1/drivers/iommu/
Dhyperv-iommu.c1 // SPDX-License-Identifier: GPL-2.0
4 * Hyper-V stub IOMMU driver.
18 #include <asm/cpu.h>
30 * According 82093AA IO-APIC spec , IO APIC has a 24-entry Interrupt
31 * Redirection Table. Hyper-V exposes one single IO-APIC and so define
42 struct irq_data *parent = data->parent_data; in hyperv_ir_set_affinity()
43 struct irq_cfg *cfg = irqd_cfg(data); in hyperv_ir_set_affinity() local
48 return -EINVAL; in hyperv_ir_set_affinity()
50 ret = parent->chip->irq_set_affinity(parent, mask, force); in hyperv_ir_set_affinity()
54 send_cleanup_vector(cfg); in hyperv_ir_set_affinity()
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/Linux-v6.1/arch/x86/platform/uv/
Duv_irq.c27 static void uv_program_mmr(struct irq_cfg *cfg, struct uv_irq_2_mmr_pnode *info) in uv_program_mmr() argument
37 entry->vector = cfg->vector; in uv_program_mmr()
38 entry->delivery_mode = apic->delivery_mode; in uv_program_mmr()
39 entry->dest_mode = apic->dest_mode_logical; in uv_program_mmr()
40 entry->polarity = 0; in uv_program_mmr()
41 entry->trigger = 0; in uv_program_mmr()
42 entry->mask = 0; in uv_program_mmr()
43 entry->dest = cfg->dest_apicid; in uv_program_mmr()
45 uv_write_global_mmr64(info->pnode, info->offset, mmr_value); in uv_program_mmr()
54 struct irq_data *parent = data->parent_data; in uv_set_irq_affinity()
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/Linux-v6.1/arch/arm/mach-versatile/
Ddcscb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * dcscb.c - Dual Cluster System Configuration Block
6 * Copyright: (C) 2012-2013 Linaro Limited
15 #include <linux/arm-cci.h>
18 #include <asm/proc-fns.h>
39 static int dcscb_cpu_powerup(unsigned int cpu, unsigned int cluster) in dcscb_cpu_powerup() argument
41 unsigned int rst_hold, cpumask = (1 << cpu); in dcscb_cpu_powerup()
43 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); in dcscb_cpu_powerup()
45 return -EINVAL; in dcscb_cpu_powerup()
59 return -EINVAL; in dcscb_cluster_powerup()
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/Linux-v6.1/arch/x86/events/
Drapl.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Intel RAPL interface is specified in the IA-32 Manual Vol3b
34 * gpu counter: consumption of the builtin-gpu domain (client only)
38 * psys counter: consumption of the builtin-psys domain (client only)
42 * We manage those counters as free running (read-only). They may be
45 * The events only support system-wide mode counting. There is no
49 * Because we want to avoid floating-point operations in the kernel,
53 * ldexp(raw_count, -32);
63 #include <asm/intel-family.h>
84 "pp0-core",
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