| /Linux-v5.10/Documentation/scheduler/ |
| D | sched-capacity.rst | 2 Capacity Aware Scheduling
5 1. CPU Capacity
9 ----------------
13 different performance characteristics - on such platforms, not all CPUs can be
16 CPU capacity is a measure of the performance a CPU can reach, normalized against
17 the most performant CPU in the system. Heterogeneous systems are also called
18 asymmetric CPU capacity systems, as they contain CPUs of different capacities.
20 Disparity in maximum attainable performance (IOW in maximum CPU capacity) stems
23 - not all CPUs may have the same microarchitecture (µarch).
24 - with Dynamic Voltage and Frequency Scaling (DVFS), not all CPUs may be
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| D | sched-energy.rst | 6 ---------------
10 Energy Model (EM) of the CPUs to select an energy efficient CPU for each task,
17 /!\ EAS does not support platforms with symmetric CPU topologies /!\
19 EAS operates only on heterogeneous CPU topologies (such as Arm big.LITTLE)
25 please refer to its documentation (see Documentation/power/energy-model.rst).
29 -----------------------------
32 - energy = [joule] (resource like a battery on powered devices)
33 - power = energy/time = [joule/second] = [watt]
39 --------------------
45 -----------
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| /Linux-v5.10/Documentation/devicetree/bindings/arm/ |
| D | cpu-capacity.txt | 2 ARM CPUs capacity bindings
6 1 - Introduction
15 2 - CPU capacity definition
18 CPU capacity is a number that provides the scheduler information about CPUs
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
25 CPU capacities are obtained by running a suitable benchmark. This binding makes
27 final capacity should, however, be:
29 * A "single-threaded" or CPU affine benchmark
30 * Divided by the running frequency of the CPU executing the benchmark
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| D | cpus.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15 defining properties for every cpu.
17 Bindings for CPU nodes follow the Devicetree Specification, available from:
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
34 cpus and cpu node bindings definition
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| /Linux-v5.10/arch/arm/kernel/ |
| D | topology.c | 15 #include <linux/cpu.h>
29 #include <asm/cpu.h>
34 * cpu capacity scale management
38 * cpu capacity table
39 * This per cpu data structure describes the relative capacity of each core.
40 * On a heteregenous system, cores don't have the same computation capacity
42 * can take this difference into account during load balance. A per cpu
43 * structure is preferred because each CPU updates its own cpu_capacity field
61 * is used to compute the capacity of a CPU.
66 {"arm,cortex-a15", 3891},
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| /Linux-v5.10/arch/arm/boot/dts/ |
| D | exynos5420-cpus.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5420 SoC cpu device tree source
9 * boards: CPU[0123] being the A15.
11 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
16 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
17 * from the LITTLE: Cortex-A7.
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu0: cpu@0 {
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| D | exynos5422-cpus.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5422 SoC cpu device tree source
8 * This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
10 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16 * from the LITTLE: Cortex-A7.
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu0: cpu@100 {
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| D | vexpress-v2p-ca15_a7.dts | 1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
8 * HBI-0249A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15_CA7";
18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
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| /Linux-v5.10/drivers/base/ |
| D | arch_topology.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Arch specific cpu topology information
10 #include <linux/cpu.h>
61 void topology_set_cpu_scale(unsigned int cpu, unsigned long capacity) in topology_set_cpu_scale() argument
63 per_cpu(cpu_scale, cpu) = capacity; in topology_set_cpu_scale()
71 int cpu; in topology_set_thermal_pressure() local
73 for_each_cpu(cpu, cpus) in topology_set_thermal_pressure()
74 WRITE_ONCE(per_cpu(thermal_pressure, cpu), th_pressure); in topology_set_thermal_pressure()
81 struct cpu *cpu = container_of(dev, struct cpu, dev); in cpu_capacity_show() local
83 return sysfs_emit(buf, "%lu\n", topology_get_cpu_scale(cpu->dev.id)); in cpu_capacity_show()
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| /Linux-v5.10/arch/arm64/boot/dts/amlogic/ |
| D | meson-g12b.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12.dtsi"
13 #address-cells = <0x2>;
14 #size-cells = <0x0>;
16 cpu-map {
19 cpu = <&cpu0>;
23 cpu = <&cpu1>;
29 cpu = <&cpu100>;
33 cpu = <&cpu101>;
37 cpu = <&cpu102>;
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| /Linux-v5.10/arch/arm64/boot/dts/qcom/ |
| D | sdm660.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
11 interrupt-parent = <&intc>;
13 #address-cells = <2>;
14 #size-cells = <2>;
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <19200000>;
23 clock-output-names = "xo_board";
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| D | sdm630.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
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| /Linux-v5.10/arch/arm64/boot/dts/arm/ |
| D | juno-r2.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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| D | juno.dts | 4 * Copyright (c) 2013-2014 ARM Ltd.
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
26 stdout-path = "serial0:115200n8";
30 compatible = "arm,psci-0.2";
35 #address-cells = <2>;
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| D | juno-r1.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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| /Linux-v5.10/include/linux/sched/ |
| D | sd_flags.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sched-domains (multiprocessor balancing) flag declarations.
29 * certain level (e.g. domain starts spanning CPUs outside of the base CPU's
78 * Consider waking task on waking CPU.
85 * Domain members have different CPU capacities
89 * NEEDS_GROUPS: Per-CPU capacity is asymmetric between groups.
94 * Domain members share CPU capacity (i.e. SMT)
97 * CPU capacity.
98 * NEEDS_GROUPS: Capacity is shared between groups.
103 * Domain members share CPU package resources (i.e. caches)
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| /Linux-v5.10/kernel/sched/ |
| D | fair.c | 1 // SPDX-License-Identifier: GPL-2.0
26 * Targeted preemption latency for CPU-bound tasks:
29 * 'timeslice length' - timeslices in CFS are of variable length
30 * and have no persistent notion like in traditional, time-slice
34 * run vmstat and monitor the context-switches (cs) field)
42 * The initial- and re-scaling of tunables is configurable
46 * SCHED_TUNABLESCALING_NONE - unscaled, always *1
47 * SCHED_TUNABLESCALING_LOG - scaled logarithmical, *1+ilog(ncpus)
48 * SCHED_TUNABLESCALING_LINEAR - scaled linear, *ncpus
55 * Minimal preemption granularity for CPU-bound tasks:
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| D | topology.c | 1 // SPDX-License-Identifier: GPL-2.0
34 static int sched_domain_debug_one(struct sched_domain *sd, int cpu, int level, in sched_domain_debug_one() argument
37 struct sched_group *group = sd->groups; in sched_domain_debug_one()
38 unsigned long flags = sd->flags; in sched_domain_debug_one()
43 printk(KERN_DEBUG "%*s domain-%d: ", level, "", level); in sched_domain_debug_one()
45 cpumask_pr_args(sched_domain_span(sd)), sd->name); in sched_domain_debug_one()
47 if (!cpumask_test_cpu(cpu, sched_domain_span(sd))) { in sched_domain_debug_one()
48 printk(KERN_ERR "ERROR: domain->span does not contain CPU%d\n", cpu); in sched_domain_debug_one()
50 if (group && !cpumask_test_cpu(cpu, sched_group_span(group))) { in sched_domain_debug_one()
51 printk(KERN_ERR "ERROR: domain->groups does not contain CPU%d\n", cpu); in sched_domain_debug_one()
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| /Linux-v5.10/Documentation/admin-guide/pm/ |
| D | cpufreq.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 CPU Performance Scaling
15 The Concept of CPU Performance Scaling
20 Operating Performance Points or P-states (in ACPI terminology). As a rule,
22 can be retired by the CPU over a unit of time, but also the higher the clock
24 time (or the more power is drawn) by the CPU in the given P-state. Therefore
25 there is a natural tradeoff between the CPU capacity (the number of instructions
26 that can be executed over a unit of time) and the power drawn by the CPU.
29 as possible and then there is no reason to use any P-states different from the
30 highest one (i.e. the highest-performance frequency/voltage configuration
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| /Linux-v5.10/include/uapi/linux/sched/ |
| D | types.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
45 * Sporadic Time-Constrained Task Attributes
48 * A subset of sched_attr attributes allows to describe a so-called
49 * sporadic time-constrained task.
52 * - the activation period or minimum instance inter-arrival time;
53 * - the maximum (or average, depending on the actual scheduling
55 * - the deadline (relative to the actual activation time) of each
58 * some specific computation --which is typically called an instance--
90 * represents the percentage of CPU time used by a task when running at the
91 * maximum frequency on the highest capacity CPU of the system. For example, a
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| /Linux-v5.10/arch/powerpc/platforms/pseries/ |
| D | lparcfg.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * keyword - value pairs that specify the configuration of the partition.
93 * R4 = Entitled Processor Capacity Percentage.
94 * R5 = Unallocated Processor Capacity Percentage.
96 * XXXX - reserved (0)
97 * XXXX - reserved (0)
98 * XXXX - Group Number
99 * XXXX - Pool Number.
101 * XX - reserved. (0)
102 * XX - bit 0-6 reserved (0). bit 7 is Capped indicator.
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| /Linux-v5.10/arch/arm64/boot/dts/mediatek/ |
| D | mt8183.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/reset-controller/mt8183-resets.h>
12 #include <dt-bindings/phy/phy.h>
13 #include "mt8183-pinfunc.h"
17 interrupt-parent = <&sysirq>;
18 #address-cells = <2>;
19 #size-cells = <2>;
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| /Linux-v5.10/include/linux/ |
| D | energy_model.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
14 * em_perf_state - Performance state of a performance domain
16 * @power: The power consumed at this level, in milli-watts (by 1 CPU or
29 * em_perf_domain - Performance domain
37 * In case of CPU device, a "performance domain" represents a group of CPUs
39 * must have the same micro-architecture. Performance domains often have
40 * a 1-to-1 mapping with CPUFreq policies. In case of other devices the @cpus
49 #define em_span_cpus(em) (to_cpumask((em)->cpus))
56 * active_power() - Provide power at the next performance state of
62 * @dev : Device for which we do this operation (can be a CPU)
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| /Linux-v5.10/Documentation/devicetree/bindings/thermal/ |
| D | thermal-idle.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/thermal/thermal-idle.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Daniel Lezcano <daniel.lezcano@linaro.org>
22 const: thermal-idle
24 A thermal-idle node describes the idle cooling device properties to
27 '#cooling-cells':
31 the cooling-maps reference. The first cell is the minimum cooling state
34 duration-us:
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| /Linux-v5.10/arch/s390/kernel/ |
| D | sysinfo.c | 1 // SPDX-License-Identifier: GPL-2.0
39 : "d" (r1), "a" (sysinfo), "K" (-EOPNOTSUPP) in __stsi()
46 * stsi - store system information
70 case 2: /* UTF-8 */ in convert_ext_name()
84 EBCASC(info->manufacturer, sizeof(info->manufacturer)); in stsi_1_1_1()
85 EBCASC(info->type, sizeof(info->type)); in stsi_1_1_1()
86 EBCASC(info->model, sizeof(info->model)); in stsi_1_1_1()
87 EBCASC(info->sequence, sizeof(info->sequence)); in stsi_1_1_1()
88 EBCASC(info->plant, sizeof(info->plant)); in stsi_1_1_1()
89 EBCASC(info->model_capacity, sizeof(info->model_capacity)); in stsi_1_1_1()
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