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/Linux-v5.15/arch/arm64/boot/dts/renesas/
Dr8a774a1-beacon-rzg2m-kit.dts44 clocks = <&cpg CPG_MOD 724>,
45 <&cpg CPG_MOD 723>,
46 <&cpg CPG_MOD 722>,
56 clocks = <&cpg CPG_MOD 1005>,
57 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
58 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
59 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
60 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
61 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
62 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
[all …]
Dr8a774b1-beacon-rzg2n-kit.dts40 clocks = <&cpg CPG_MOD 724>,
41 <&cpg CPG_MOD 723>,
42 <&cpg CPG_MOD 721>,
52 clocks = <&cpg CPG_MOD 1005>,
53 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
54 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
55 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
56 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
57 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
58 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
[all …]
Dr8a774e1-beacon-rzg2h-kit.dts45 clocks = <&cpg CPG_MOD 724>,
46 <&cpg CPG_MOD 723>,
47 <&cpg CPG_MOD 721>,
57 clocks = <&cpg CPG_MOD 1005>,
58 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
59 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
60 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
61 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
62 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
63 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
[all …]
Dr8a77995.dtsi9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
97 clocks = <&cpg CPG_MOD 402>;
99 resets = <&cpg 402>;
113 clocks = <&cpg CPG_MOD 912>;
115 resets = <&cpg 912>;
128 clocks = <&cpg CPG_MOD 911>;
130 resets = <&cpg 911>;
143 clocks = <&cpg CPG_MOD 910>;
145 resets = <&cpg 910>;
158 clocks = <&cpg CPG_MOD 909>;
[all …]
Dr8a77990.dtsi8 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
93 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
105 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
174 clocks = <&cpg CPG_MOD 402>;
176 resets = <&cpg 402>;
190 clocks = <&cpg CPG_MOD 912>;
192 resets = <&cpg 912>;
205 clocks = <&cpg CPG_MOD 911>;
207 resets = <&cpg 911>;
220 clocks = <&cpg CPG_MOD 910>;
[all …]
Dhihope-rev4.dtsi99 clocks = <&cpg CPG_MOD 1005>,
100 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
101 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
102 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
103 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
104 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
105 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
106 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
107 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
108 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
[all …]
Dr8a774c0.dtsi8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
81 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
92 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
148 clocks = <&cpg CPG_MOD 402>;
150 resets = <&cpg 402>;
164 clocks = <&cpg CPG_MOD 912>;
166 resets = <&cpg 912>;
179 clocks = <&cpg CPG_MOD 911>;
181 resets = <&cpg 911>;
194 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a77951.dtsi8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
165 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
179 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
193 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
207 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
223 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
236 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
249 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
262 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
372 clocks = <&cpg CPG_MOD 402>;
[all …]
Dr8a77965.dtsi11 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
119 clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
131 clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
208 clocks = <&cpg CPG_MOD 402>;
210 resets = <&cpg 402>;
224 clocks = <&cpg CPG_MOD 912>;
226 resets = <&cpg 912>;
239 clocks = <&cpg CPG_MOD 911>;
241 resets = <&cpg 911>;
254 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a774a1.dtsi10 #include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
142 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
155 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
170 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
182 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
194 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
206 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
286 clocks = <&cpg CPG_MOD 402>;
288 resets = <&cpg 402>;
302 clocks = <&cpg CPG_MOD 912>;
[all …]
Dr8a774b1.dtsi10 #include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
85 clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
96 clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
159 clocks = <&cpg CPG_MOD 402>;
161 resets = <&cpg 402>;
175 clocks = <&cpg CPG_MOD 912>;
177 resets = <&cpg 912>;
190 clocks = <&cpg CPG_MOD 911>;
192 resets = <&cpg 911>;
205 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a77980.dtsi9 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
43 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
53 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
63 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
73 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
141 clocks = <&cpg CPG_MOD 402>;
143 resets = <&cpg 402>;
157 clocks = <&cpg CPG_MOD 912>;
159 resets = <&cpg 912>;
172 clocks = <&cpg CPG_MOD 911>;
[all …]
Dr8a77960.dtsi8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
166 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
180 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
196 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
209 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
222 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
235 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
337 clocks = <&cpg CPG_MOD 402>;
339 resets = <&cpg 402>;
353 clocks = <&cpg CPG_MOD 912>;
[all …]
/Linux-v5.15/drivers/clk/renesas/
DMakefile5 obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
8 obj-$(CONFIG_CLK_R8A7742) += r8a7742-cpg-mssr.o
9 obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
10 obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
11 obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
12 obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
13 obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o
14 obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o
15 obj-$(CONFIG_CLK_R8A774E1) += r8a774e1-cpg-mssr.o
18 obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/clock/
Drenesas,cpg-mssr.yaml4 $id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#"
13 On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
18 - The CPG block generates various core clocks,
27 - renesas,r7s9210-cpg-mssr # RZ/A2
28 - renesas,r8a7742-cpg-mssr # RZ/G1H
29 - renesas,r8a7743-cpg-mssr # RZ/G1M
30 - renesas,r8a7744-cpg-mssr # RZ/G1N
31 - renesas,r8a7745-cpg-mssr # RZ/G1E
32 - renesas,r8a77470-cpg-mssr # RZ/G1C
33 - renesas,r8a774a1-cpg-mssr # RZ/G2M
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Dr8a7791.dtsi10 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
77 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
98 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
164 clocks = <&cpg CPG_MOD 402>;
166 resets = <&cpg 402>;
180 clocks = <&cpg CPG_MOD 912>;
182 resets = <&cpg 912>;
195 clocks = <&cpg CPG_MOD 911>;
197 resets = <&cpg 911>;
210 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7792.dtsi8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
54 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
65 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
114 clocks = <&cpg CPG_MOD 402>;
116 resets = <&cpg 402>;
130 clocks = <&cpg CPG_MOD 912>;
132 resets = <&cpg 912>;
145 clocks = <&cpg CPG_MOD 911>;
147 resets = <&cpg 911>;
160 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7745.dtsi10 #include <dt-bindings/clock/r8a7745-cpg-mssr.h>
73 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
84 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
139 clocks = <&cpg CPG_MOD 912>;
141 resets = <&cpg 912>;
154 clocks = <&cpg CPG_MOD 911>;
156 resets = <&cpg 911>;
169 clocks = <&cpg CPG_MOD 910>;
171 resets = <&cpg 910>;
184 clocks = <&cpg CPG_MOD 909>;
[all …]
Dr8a77470.dtsi10 #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
34 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
45 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
94 clocks = <&cpg CPG_MOD 402>;
96 resets = <&cpg 402>;
110 clocks = <&cpg CPG_MOD 912>;
112 resets = <&cpg 912>;
125 clocks = <&cpg CPG_MOD 911>;
127 resets = <&cpg 911>;
140 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7793.dtsi8 #include <dt-bindings/clock/r8a7793-cpg-mssr.h>
69 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
90 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
149 clocks = <&cpg CPG_MOD 402>;
151 resets = <&cpg 402>;
165 clocks = <&cpg CPG_MOD 912>;
167 resets = <&cpg 912>;
180 clocks = <&cpg CPG_MOD 911>;
182 resets = <&cpg 911>;
195 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7794.dtsi9 #include <dt-bindings/clock/r8a7794-cpg-mssr.h>
71 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
82 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
131 clocks = <&cpg CPG_MOD 402>;
133 resets = <&cpg 402>;
147 clocks = <&cpg CPG_MOD 912>;
149 resets = <&cpg 912>;
162 clocks = <&cpg CPG_MOD 911>;
164 resets = <&cpg 911>;
177 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7742.dtsi8 #include <dt-bindings/clock/r8a7742-cpg-mssr.h>
56 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
78 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
100 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
122 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
144 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
154 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
164 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
174 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
248 clocks = <&cpg CPG_MOD 402>;
[all …]
Dr8a7743.dtsi10 #include <dt-bindings/clock/r8a7743-cpg-mssr.h>
58 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
78 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
143 clocks = <&cpg CPG_MOD 402>;
145 resets = <&cpg 402>;
159 clocks = <&cpg CPG_MOD 912>;
161 resets = <&cpg 912>;
174 clocks = <&cpg CPG_MOD 911>;
176 resets = <&cpg 911>;
189 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7744.dtsi10 #include <dt-bindings/clock/r8a7744-cpg-mssr.h>
58 clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
78 clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
143 clocks = <&cpg CPG_MOD 402>;
145 resets = <&cpg 402>;
159 clocks = <&cpg CPG_MOD 912>;
161 resets = <&cpg 912>;
174 clocks = <&cpg CPG_MOD 911>;
176 resets = <&cpg 911>;
189 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7790.dtsi10 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
78 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
100 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
122 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
144 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
166 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
178 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
190 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
202 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
277 clocks = <&cpg CPG_MOD 402>;
[all …]

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