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/Linux-v5.10/Documentation/devicetree/bindings/clock/
Drenesas,cpg-div6-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas CPG DIV6 Clock
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
14 Generator (CPG). Their clock input is divided by a configurable factor from 1
20 - enum:
21 - renesas,r8a73a4-div6-clock # R-Mobile APE6
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/Linux-v5.10/arch/arm/boot/dts/
Dsh73a0.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC
8 #include <dt-bindings/clock/sh73a0-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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Dr8a73a4.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/r8a73a4-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a15";
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Dr8a7740.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Mobile A1 (R8A77400) SoC
8 #include <dt-bindings/clock/r8a7740-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/Linux-v5.10/drivers/clk/renesas/
Dclk-div6.c1 // SPDX-License-Identifier: GPL-2.0
3 * r8a7790 Common Clock Framework support
10 #include <linux/clk-provider.h>
20 #include "clk-div6.h"
27 * struct div6_clock - CPG 6 bit divider clock
28 * @hw: handle between common and hardware-specific interfaces
29 * @reg: IO-remapped register
30 * @div: divisor value (1-64)
31 * @src_shift: Shift to access the register bits to select the parent clock
32 * @src_width: Number of register bits to select the parent clock (may be 0)
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Drenesas-cpg-mssr.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Renesas Clock Pulse Generator / Module Standby and Software Reset
12 * Definitions of CPG Core Clocks
15 * - Clock outputs exported to DT
16 * - External input clocks
17 * - Internal CPG clocks
34 CLK_TYPE_IN, /* External Clock Input */
35 CLK_TYPE_FF, /* Fixed Factor Clock */
36 CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
37 CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 obj-$(CONFIG_CLK_EMEV2) += clk-emev2.o
4 obj-$(CONFIG_CLK_RZA1) += clk-rz.o
5 obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
6 obj-$(CONFIG_CLK_R8A73A4) += clk-r8a73a4.o
7 obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o
8 obj-$(CONFIG_CLK_R8A7742) += r8a7742-cpg-mssr.o
9 obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
10 obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
11 obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
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DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS
41 bool "Emma Mobile EV2 clock support" if COMPILE_TEST
44 bool "RZ/A1H clock support" if COMPILE_TEST
48 bool "RZ/A2 clock support" if COMPILE_TEST
52 bool "R-Mobile APE6 clock support" if COMPILE_TEST
57 bool "R-Mobile A1 clock support" if COMPILE_TEST
62 bool "RZ/G1H clock support" if COMPILE_TEST
66 bool "RZ/G1M clock support" if COMPILE_TEST
70 bool "RZ/G1E clock support" if COMPILE_TEST
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Drenesas-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas Clock Pulse Generator / Module Standby and Software Reset
7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
14 #include <linux/clk-provider.h>
28 #include <linux/reset-controller.h>
31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
33 #include "renesas-cpg-mssr.h"
34 #include "clk-div6.h"
46 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
47 * R-Car Gen2, R-Car Gen3, and RZ/G1.
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/Linux-v5.10/Documentation/devicetree/bindings/net/can/
Drcar_canfd.txt1 Renesas R-Car CAN FD controller Device Tree Bindings
2 ----------------------------------------------------
5 - compatible: Must contain one or more of the following:
6 - "renesas,rcar-gen3-canfd" for R-Car Gen3 and RZ/G2 compatible controllers.
7 - "renesas,r8a774a1-canfd" for R8A774A1 (RZ/G2M) compatible controller.
8 - "renesas,r8a774b1-canfd" for R8A774B1 (RZ/G2N) compatible controller.
9 - "renesas,r8a774c0-canfd" for R8A774C0 (RZ/G2E) compatible controller.
10 - "renesas,r8a774e1-canfd" for R8A774E1 (RZ/G2H) compatible controller.
11 - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
12 - "renesas,r8a7796-canfd" for R8A7796 (R-Car M3-W) compatible controller.
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/Linux-v5.10/drivers/sh/clk/
Dcpg.c2 * Helper routines for SuperH Clock Pulse Generator blocks (CPG).
5 * Copyright (C) 2010 - 2012 Paul Mundt
21 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_read()
22 return ioread8(clk->mapped_reg); in sh_clk_read()
23 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_read()
24 return ioread16(clk->mapped_reg); in sh_clk_read()
26 return ioread32(clk->mapped_reg); in sh_clk_read()
31 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_write()
32 iowrite8(value, clk->mapped_reg); in sh_clk_write()
33 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_write()
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