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/Linux-v5.10/Documentation/devicetree/bindings/timer/
Darm,global_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,global_timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Global Timer
10 - Stuart Menefy <stuart.menefy@st.com>
13 Cortex-A9 are often associated with a per-core Global timer.
18 - enum:
19 - arm,cortex-a5-global-timer
20 - arm,cortex-a9-global-timer
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Dowl-s500.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright (c) 2016-2017 Andreas Färber
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/power/owl-s500-powergate.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <0>;
29 compatible = "arm,cortex-a9";
[all …]
Dbcm63138.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&gic>;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
[all …]
Dvf500.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a5";
28 intc: interrupt-controller@40003000 {
29 compatible = "arm,cortex-a9-gic";
30 #interrupt-cells = <3>;
[all …]
Dhip01.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
12 interrupt-parent = <&gic>;
13 #address-cells = <1>;
14 #size-cells = <1>;
16 gic: interrupt-controller@1e001000 {
17 compatible = "arm,cortex-a9-gic";
18 #interrupt-cells = <3>;
19 #address-cells = <0>;
20 interrupt-controller;
25 compatible = "fixed-clock";
[all …]
Dzx296702.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/zx296702-clock.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
13 enable-method = "zte,zx296702-smp";
16 compatible = "arm,cortex-a9";
18 next-level-cache = <&l2cc>;
[all …]
Dberlin2cd.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Marvell Armada 1500-mini (BG2CD) SoC";
17 #address-cells = <1>;
18 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a9";
[all …]
Dbcm-hr2.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
39 interrupt-parent = <&gic>;
40 #address-cells = <1>;
41 #size-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <0>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
56 compatible = "arm,cortex-a9-pmu";
[all …]
Dvexpress-v2p-ca5s.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A5 MPCore (V2P-CA5s)
8 * HBI-0225B
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA5s";
18 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
[all …]
Dartpec6.dtsi2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
[all …]
Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
[all …]
Dmeson8.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8-gpio.h>
9 #include <dt-bindings/power/meson8-power.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
19 #address-cells = <1>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-a9";
[all …]
Drk3xxx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&gic>;
36 compatible = "simple-bus";
37 #address-cells = <1>;
38 #size-cells = <1>;
[all …]
Dbcm5301x.dtsi6 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
11 #include <dt-bindings/clock/bcm-nsp.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
20 interrupt-parent = <&gic>;
23 compatible = "simple-bus";
[all …]
Dbcm-nsp.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
42 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <0>;
58 compatible = "arm,cortex-a9";
59 next-level-cache = <&L2>;
[all …]
Dr8a7779.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H1 (R8A77790) SoC
9 #include <dt-bindings/clock/r8a7779-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a7779-sysc.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
21 #address-cells = <1>;
[all …]
Duniphier-ld4.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
11 compatible = "socionext,uniphier-ld4";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
[all …]
Duniphier-sld8.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
11 compatible = "socionext,uniphier-sld8";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
[all …]
Dam4372.dtsi4 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
11 #include <dt-bindings/bus/ti-sysc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/clock/am4.h>
18 interrupt-parent = <&wakeupgen>;
19 #address-cells = <1>;
20 #size-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <0>;
[all …]
Darmada-38x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
32 compatible = "arm,cortex-a9-pmu";
33 interrupts-extended = <&mpic 3>;
37 compatible = "marvell,armada380-mbus", "simple-bus";
[all …]
Duniphier-pxs2.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/thermal/thermal.h>
12 compatible = "socionext,uniphier-pxs2";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
[all …]
Duniphier-pro4.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
11 compatible = "socionext,uniphier-pro4";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
[all …]
Duniphier-pro5.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
9 compatible = "socionext,uniphier-pro5";
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
22 enable-method = "psci";
23 next-level-cache = <&l2>;
[all …]
Dstih407-family.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih407-pinctrl.dtsi"
7 #include <dt-bindings/mfd/st-lpc.h>
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/reset/stih407-resets.h>
10 #include <dt-bindings/interrupt-controller/irq-st.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 reserved-memory {
16 #address-cells = <1>;
[all …]
/Linux-v5.10/drivers/clocksource/
Darm_global_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
54 * To get the value from the Global Timer Counter register proceed as follows:
55 * 1. Read the upper 32-bit timer counter register
56 * 2. Read the lower 32-bit timer counter register
57 * 3. Read the upper 32-bit timer counter register again. If the value is
58 * different to the 32-bit upper value read previously, go back to step 2.
59 * Otherwise the 64-bit timer counter value is correct.
88 * 1. Clear the Comp Enable bit in the Timer Control Register.
89 * 2. Write the lower 32-bit Comparator Value Register.
90 * 3. Write the upper 32-bit Comparator Value Register.
[all …]

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