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/Linux-v5.10/arch/arm/mach-realview/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
34 the ARM926EJ-S core tile, while on an ARMv6/v7 kernel, at least
35 one of the ARM1136, ARM1176, ARM11MPCore or Cortex-A9MPCore
39 bool "Support ARM1136J(F)-S Tile"
47 bool "Support ARM1176JZ(F)-S Tile"
54 bool "Support Multicore Cortex-A9 Tile"
57 Enable support for the Cortex-A9MPCore tile fitted to the
74 the ARM11MPCore. This platform has an on-board ARM11MPCore and has
75 support for PCI-E and Compact Flash.
79 bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S"
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/arm/
Darm,realview.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
14 11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to
22 - description: ARM RealView Emulation Baseboard (HBI-0140) was created
26 - const: arm,realview-eb
27 - description: ARM RealView Platform Baseboard for ARM1176JZF-S
28 (HBI-0147) was created as a development board to test ARM TrustZone,
31 - const: arm,realview-pb1176
[all …]
Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
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Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - arm,armv8-pmuv3 # Only for s/w models
24 - arm,arm1136-pmu
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/Linux-v5.10/arch/arm/boot/dts/
Darm-realview-pba8.dts23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
27 model = "ARM RealView Platform Baseboard for Cortex-A8";
28 compatible = "arm,realview-pba8";
32 #address-cells = <1>;
33 #size-cells = <0>;
34 enable-method = "arm,realview-smp";
38 compatible = "arm,cortex-a8";
44 compatible = "arm,cortex-a8-pmu";
45 interrupt-parent = <&intc>;
[all …]
Dcx92755.dtsi8 * This file is dual-licensed: you can use it either under the terms
48 #address-cells = <1>;
49 #size-cells = <1>;
52 interrupt-parent = <&intc>;
55 #address-cells = <1>;
56 #size-cells = <0>;
59 compatible = "arm,cortex-a8";
65 compatible = "fixed-clock";
66 #clock-cells = <0>;
67 clock-frequency = <200000000>;
[all …]
Dmeson8.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8-gpio.h>
9 #include <dt-bindings/power/meson8-power.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
19 #address-cells = <1>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-a9";
[all …]
Dmeson8b.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/power/meson8-power.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a5";
[all …]
Dimx51.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include "imx51-pinfunc.h"
7 #include <dt-bindings/clock/imx5-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
17 * pre-existing /chosen node to be available to insert the
42 tzic: tz-interrupt-controller@e0000000 {
[all …]
Dam33xx.dtsi4 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
11 #include <dt-bindings/bus/ti-sysc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/pinctrl/am33xx.h>
14 #include <dt-bindings/clock/am3.h>
18 interrupt-parent = <&intc>;
19 #address-cells = <1>;
20 #size-cells = <1>;
33 d-can0 = &dcan0;
34 d-can1 = &dcan1;
[all …]
Ddm816x.dtsi7 #include <dt-bindings/bus/ti-sysc.h>
8 #include <dt-bindings/clock/dm816.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/omap.h>
14 interrupt-parent = <&intc>;
15 #address-cells = <1>;
16 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
33 compatible = "arm,cortex-a8";
[all …]
Ddm814x.dtsi7 #include <dt-bindings/bus/ti-sysc.h>
8 #include <dt-bindings/clock/dm814.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/dm814x.h>
14 interrupt-parent = <&intc>;
15 #address-cells = <1>;
16 #size-cells = <1>;
34 #address-cells = <1>;
35 #size-cells = <0>;
37 compatible = "arm,cortex-a8";
[all …]
Dimx53.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include "imx53-pinfunc.h"
7 #include <dt-bindings/clock/imx5-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
17 * pre-existing /chosen node to be available to insert the
50 #address-cells = <1>;
[all …]
Domap3.dtsi4 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
11 #include <dt-bindings/bus/ti-sysc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/pinctrl/omap.h>
18 interrupt-parent = <&intc>;
19 #address-cells = <1>;
20 #size-cells = <1>;
33 #address-cells = <1>;
34 #size-cells = <0>;
[all …]
/Linux-v5.10/arch/arm/mm/
Dproc-v7.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7.S
9 #include <linux/arm-smccc.h>
14 #include <asm/asm-offsets.h>
16 #include <asm/pgtable-hwdef.h>
19 #include "proc-macros.S"
22 #include "proc-v7-3level.S"
24 #include "proc-v7-2level.S"
46 * - loc - location to jump to for soft reset
47 * - hyp - indicate if restart occurs in HYP mode
[all …]
Dproc-v7-2level.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/mm/proc-v7-2level.S
32 * - pgd_phys - physical address of new TTB
35 * - we are not using split page tables
38 * even on Cortex-A8 revisions not affected by 430973.
43 mmid r1, r1 @ get mm->context.id
67 * - ptep - pointer to level 2 translation table entry
69 * - pte - PTE value to store
70 * - ext - value for extended PTE bits
113 * TR = PRRR[2n+1:2n] - memory type
[all …]
/Linux-v5.10/Documentation/arm/
Dsunxi.rst10 ------------
11 Linux kernel mach directory: arch/arm/mach-sunxi
16 - Allwinner F20 (sun3i)
20 * ARM Cortex-A8 based SoCs
21 - Allwinner A10 (sun4i)
25 http://dl.linux-sunxi.org/A10/A10%20Datasheet%20-%20v1.21%20%282012-04-06%29.pdf
28 …http://dl.linux-sunxi.org/A10/A10%20User%20Manual%20-%20v1.20%20%282012-04-09%2c%20DECRYPTED%29.pdf
30 - Allwinner A10s (sun5i)
34 http://dl.linux-sunxi.org/A10s/A10s%20Datasheet%20-%20v1.20%20%282012-03-27%29.pdf
36 - Allwinner A13 / R8 (sun5i)
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/Linux-v5.10/arch/arm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
129 The ARM series is a line of low-power-consumption RISC chip designs
131 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
132 manufactured, but legacy ARM-based PC hardware remains popular in
242 Patch phys-to-virt and virt-to-phys translation functions at
246 This can only be used with non-XIP MMU kernels where the base
292 bool "MMU-based Paged Memory Management Support"
295 Select if you want MMU-based virtualised addressing space
334 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
347 bool "EBSA-110"
[all …]
/Linux-v5.10/arch/arm/mach-imx/
Dcpu-imx5.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
19 static int mx5_cpu_rev = -1;
42 u32 rev = imx5_read_srev_reg("fsl,imx51-iim"); in get_mx51_srev()
60 if (mx5_cpu_rev == -1) in mx51_revision()
71 * Dependent on link order - so the assumption is that vfp_init is called
88 u32 rev = imx5_read_srev_reg("fsl,imx53-iim"); in get_mx53_srev()
108 if (mx5_cpu_rev == -1) in mx53_revision()
134 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu"); in imx5_pmu_init()
138 if (!of_property_read_bool(np, "secure-reg-access")) in imx5_pmu_init()
[all …]
/Linux-v5.10/arch/arm/kernel/
Dperf_event_v7.c1 // SPDX-License-Identifier: GPL-2.0
3 * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code.
11 * Cortex-A8 has up to 4 configurable performance counters and
13 * Cortex-A9 has up to 31 configurable performance counters and
55 * - all (taken) branch instructions,
56 * - instructions that explicitly write the PC,
57 * - exception generating instructions.
82 /* ARMv7 Cortex-A8 specific event types */
88 /* ARMv7 Cortex-A9 specific event types */
93 /* ARMv7 Cortex-A5 specific event types */
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/cpufreq/
Dti-cpufreq.txt6 The ti-cpufreq driver can use revision and an efuse value from the SoC to
8 used to determine which OPPs from the operating-points-v2 table get enabled
12 --------------------
14 - operating-points-v2: Phandle to the operating-points-v2 table to use.
16 In 'operating-points-v2' table:
17 - compatible: Should be
18 - 'operating-points-v2-ti-cpu' for am335x, am43xx, and dra7xx/am57xx,
20 - syscon: A phandle pointing to a syscon node representing the control module
24 --------------------
25 - "vdd-supply", "vbb-supply": to define two regulators for dra7xx
[all …]
/Linux-v5.10/arch/arm/crypto/
Dsha512-armv4.pl2 # SPDX-License-Identifier: GPL-2.0
22 # by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue
27 # Rescheduling for dual-issue pipeline resulted in 6% improvement on
28 # Cortex A8 core and ~40 cycles per processed byte.
32 # Profiler-assisted and platform-specific optimization resulted in 7%
33 # improvement on Coxtex A8 core and ~38 cycles per byte.
37 # Add NEON implementation. On Cortex A8 it was measured to process
38 # one byte in 23.3 cycles or ~60% faster than integer-only code.
44 # Technical writers asserted that 3-way S4 pipeline can sustain
46 # not be observed, see https://www.openssl.org/~appro/Snapdragon-S4.html
[all …]
Dsha1-armv4-large.S2 @ SPDX-License-Identifier: GPL-2.0
23 @ Size/performance trade-off
28 @ armv4-small 392/+29% 1958/+64% 2250/+96%
29 @ armv4-compact 740/+89% 1552/+26% 1840/+22%
30 @ armv4-large 1420/+92% 1307/+19% 1370/+34%[***]
42 @ i-cache availability, branch penalties, etc.
49 @ [***] which is also ~35% better than compiler generated code. Dual-
50 @ issue Cortex A8 core was measured to process input block in
55 @ Rescheduling for dual-issue pipeline resulted in 13% improvement on
56 @ Cortex A8 core and in absolute terms ~870 cycles per input block
[all …]
Dsha256-armv4.pl2 # SPDX-License-Identifier: GPL-2.0
21 # Performance is ~2x better than gcc 3.4 generated code and in "abso-
22 # lute" terms is ~2250 cycles per 64-byte block or ~35 cycles per
23 # byte [on single-issue Xscale PXA250 core].
27 # Rescheduling for dual-issue pipeline resulted in 22% improvement on
28 # Cortex A8 core and ~20 cycles per processed byte.
32 # Profiler-assisted and platform-specific optimization resulted in 16%
33 # improvement on Cortex A8 core and ~15.4 cycles per processed byte.
37 # Add NEON implementation. On Cortex A8 it was measured to process one
38 # byte in 12.5 cycles or 23% faster than integer-only code. Snapdragon
[all …]
/Linux-v5.10/arch/arm/mach-omap2/
Dsleep33xx.S1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2012-2018 Texas Instruments Incorporated - https://www.ti.com/
11 #include <linux/ti-emif-sram.h>
17 #include "pm-asm-offsets.h"
27 .arch armv7-a
31 stmfd sp!, {r4 - r11, lr} @ save registers on stack
140 * NOPs as per Cortex-A8 pipeline.
165 /* Re-enable EMIF */
197 ldmfd sp!, {r4 - r11, pc} @ restore regs and return
202 .word . - am33xx_do_wfi
[all …]

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