coresight (full) in projects: Linux-v5.15

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/Linux-v5.15/drivers/hwtracing/coresight/
D	Makefile	3 # Makefile for CoreSight drivers. 5 obj-$(CONFIG_CORESIGHT) += coresight.o 6 coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \ 7 coresight-sysfs.o coresight-syscfg.o coresight-config.o \ 8 coresight-cfg-preload.o coresight-cfg-afdo.o \ 9 coresight-syscfg-configfs.o 10 obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o 11 coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \ 12 coresight-tmc-etr.o 13 obj-$(CONFIG_CORESIGHT_SINK_TPIU) += coresight-tpiu.o [all …]
D	Kconfig	`3 # Coresight configuration 5 menuconfig CORESIGHT config 6 tristate "CoreSight Tracing Support" 13 This framework provides a kernel interface for the CoreSight debug 15 a topological view of the CoreSight components based on a DT 20 module will be called coresight. 22 if CORESIGHT 24 tristate "CoreSight Link and Sink drivers" 26 This enables support for CoreSight link and sink drivers that are 32 modules will be called coresight-funnel and coresight-replicator. [all …]`
D	coresight-syscfg.h	`3 * Coresight system configuration driver. 10 #include <linux/coresight.h> 13 #include "coresight-config.h" 18 * Contains lists of the loaded configurations and features, plus a list of CoreSight devices 21 * Need a device to 'own' some coresight system wide sysfs entries in 25 * @csdev_desc_list: List of coresight devices registered with the configuration manager. 44 * List entry for Coresight devices that are registered as supporting complex`
D	coresight-syscfg.c	10 #include "coresight-config.h" 11 #include "coresight-etm-perf.h" 12 #include "coresight-syscfg.h" 13 #include "coresight-syscfg-configfs.h" 16 * cscfg_ API manages configurations and features for the entire coresight 20 * coresight devices as appropriate. 31 /* get name feature instance from a coresight device list of features / 51 / this is being allocated using the devm for the coresight device / in cscfg_alloc_csdev_cfg() 174 / load one feature into one coresight device */ 381 pr_err("coresight-syscfg: Failed to load feature %s\n", in cscfg_load_config_sets() [all …]
D	coresight-config.h	10 #include <linux/coresight.h> 13 /* CoreSight Configuration Management - component and system wide configuration / 40 See PMU_FORMAT_ATTR(preset, "config:0-3") in coresight-etm-perf.c 177 * Feature instance loaded into a CoreSight device. 188 * @csdev: parent CoreSight device instance. 208 * Configuration instance when loaded into a CoreSight device. 214 * @csdev: parent coresight device for this configuration instance. 216 * @node: list entry within the coresight device 231 * Coresight device operations. 233 * Registered coresight devices provide these operations to manage feature [all …]
/Linux-v5.15/Documentation/devicetree/bindings/arm/
D	coresight.txt	1 * CoreSight Components: 3 CoreSight components are compliant with the ARM CoreSight architecture 8 sink. Each CoreSight component device should use these properties to describe 17 "arm,coresight-etb10", "arm,primecell"; 20 "arm,coresight-tpiu", "arm,primecell"; 26 "arm,coresight-tmc", "arm,primecell"; 29 "arm,coresight-dynamic-funnel", "arm,primecell"; 30 "arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For 35 "arm,coresight-etm3x", "arm,primecell"; 38 "arm,coresight-etm4x", "arm,primecell"; [all …]
D	coresight-cti.yaml	5 $id: http://devicetree.org/schemas/arm/coresight-cti.yaml# 8 title: ARM Coresight Cross Trigger Interface (CTI) device. 11 The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected 12 to one or more CoreSight components and/or a CPU, with CTIs interconnected in 15 not part of the CoreSight graph described in the general CoreSight bindings 16 file coresight.txt. 38 indicate this feature (arm,coresight-cti-v8-arch). 49 between CTI and other CoreSight components. 51 Certain triggers between CoreSight devices and the CTI have specific types 53 constants defined in <dt-bindings/arm/coresight-cti-dt.h> [all …]
D	ete.yaml	16 allows tracing the CPU execution. It overlaps with the CoreSight ETMv4 18 The trace generated by the ETE could be stored via legacy CoreSight 21 legacy CoreSight components, a node must be listed per instance, along 22 with any optional connection graph as per the coresight bindings. 23 See bindings/arm/coresight.txt. 39 Output connections from the ETE to legacy CoreSight trace bus. 43 description: Output connection from the ETE to legacy CoreSight Trace bus. 54 # An ETE node without legacy CoreSight connections 60 # An ETE node with legacy CoreSight connections 66 out-ports { /* legacy coresight connection */
D	coresight-cpu-debug.txt	`1 * CoreSight CPU Debug Component: 3 CoreSight CPU debug component are compliant with the ARMv8 architecture 6 external debug, and it can be accessed from mmio region from Coresight 14 - compatible : should be "arm,coresight-cpu-debug"; supplemented with 44 compatible = "arm,coresight-cpu-debug","arm,primecell";`
/Linux-v5.15/Documentation/ABI/testing/
D	sysfs-bus-coresight-devices-etm4x	1 What: /sys/bus/coresight/devices/etm<N>/enable_source 8 of coresight components linking the source to the sink is 9 configured and managed automatically by the coresight framework. 11 What: /sys/bus/coresight/devices/etm<N>/cpu 17 What: /sys/bus/coresight/devices/etm<N>/nr_pe_cmp 24 What: /sys/bus/coresight/devices/etm<N>/nr_addr_cmp 31 What: /sys/bus/coresight/devices/etm<N>/nr_cntr 38 What: /sys/bus/coresight/devices/etm<N>/nr_ext_inp 44 What: /sys/bus/coresight/devices/etm<N>/numcidc 51 What: /sys/bus/coresight/devices/etm<N>/numvmidc [all …]
D	sysfs-bus-coresight-devices-cti	1 What: /sys/bus/coresight/devices/<cti-name>/enable 7 What: /sys/bus/coresight/devices/<cti-name>/powered 13 What: /sys/bus/coresight/devices/<cti-name>/ctmid 19 What: /sys/bus/coresight/devices/<cti-name>/nr_trigger_cons 25 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/name 31 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/in_signals 37 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/in_types 44 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/out_signals 50 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/out_types 57 What: /sys/bus/coresight/devices/<cti-name>/regs/inout_sel [all …]
D	sysfs-bus-coresight-devices-etm3x	1 What: /sys/bus/coresight/devices/<memory_map>.[etm\|ptm]/enable_source 8 of coresight components linking the source to the sink is 9 configured and managed automatically by the coresight framework. 11 What: /sys/bus/coresight/devices/<memory_map>.[etm\|ptm]/addr_idx 18 What: /sys/bus/coresight/devices/<memory_map>.[etm\|ptm]/addr_acctype 29 What: /sys/bus/coresight/devices/<memory_map>.[etm\|ptm]/addr_range 37 What: /sys/bus/coresight/devices/<memory_map>.[etm\|ptm]/addr_single 45 What: /sys/bus/coresight/devices/<memory_map>.[etm\|ptm]/addr_start 53 What: /sys/bus/coresight/devices/<memory_map>.[etm\|ptm]/addr_stop 61 What: /sys/bus/coresight/devices/<memory_map>.[etm\|ptm]/cntr_idx [all …]
D	sysfs-bus-coresight-devices-tmc	1 What: /sys/bus/coresight/devices/<memory_map>.tmc/trigger_cntr 10 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rsz 17 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/sts 24 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rrp 33 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rwp 39 the CoreSight bus into the Trace RAM. The value is read directly 42 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/trg 49 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ctl 56 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffsr 64 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffcr [all …]
D	sysfs-bus-coresight-devices-etb10	1 What: /sys/bus/coresight/devices/<memory_map>.etb/enable_sink 10 echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink 12 What: /sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr 22 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rdp 29 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/sts 36 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rrp 45 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rwp 51 the CoreSight bus into the Trace RAM. The value is read directly 54 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/trg 61 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ctl [all …]
D	sysfs-bus-coresight-devices-stm	1 What: /sys/bus/coresight/devices/<memory_map>.stm/enable_source 8 of coresight components linking the source to the sink is 9 configured and managed automatically by the coresight framework. 11 What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_enable 18 What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_select 26 What: /sys/bus/coresight/devices/<memory_map>.stm/port_enable 34 What: /sys/bus/coresight/devices/<memory_map>.stm/port_select 41 What: /sys/bus/coresight/devices/<memory_map>.stm/status 48 What: /sys/bus/coresight/devices/<memory_map>.stm/traceid
/Linux-v5.15/arch/arm64/boot/dts/hisilicon/
D	hi6220-coresight.dtsi	3 * dtsi file for Hisilicon Hi6220 coresight 14 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 39 compatible = "arm,coresight-tmc", "arm,primecell"; 64 compatible = "arm,coresight-static-replicator"; 100 compatible = "arm,coresight-tmc", "arm,primecell"; 116 compatible = "arm,coresight-tpiu", "arm,primecell"; 132 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 217 compatible = "arm,coresight-etm4x", "arm,primecell"; 236 compatible = "arm,coresight-etm4x", "arm,primecell"; 255 compatible = "arm,coresight-etm4x", "arm,primecell"; [all …]
D	hi3660-coresight.dtsi	4 * dtsi for Hisilicon Hi3660 Coresight 15 compatible = "arm,coresight-etm4x", "arm,primecell"; 32 compatible = "arm,coresight-etm4x", "arm,primecell"; 49 compatible = "arm,coresight-etm4x", "arm,primecell"; 66 compatible = "arm,coresight-etm4x", "arm,primecell"; 83 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 132 compatible = "arm,coresight-tmc", "arm,primecell"; 158 compatible = "arm,coresight-etm4x", "arm,primecell"; 175 compatible = "arm,coresight-etm4x", "arm,primecell"; 192 compatible = "arm,coresight-etm4x", "arm,primecell"; [all …]
/Linux-v5.15/Documentation/trace/coresight/
D	coresight.rst	2 Coresight - HW Assisted Tracing on ARM 11 Coresight is an umbrella of technologies allowing for the debugging of ARM 24 flows through the coresight system (via ATB bus) using links that are connecting 25 the emanating source to a sink(s). Sinks serve as endpoints to the coresight 28 host without fear of filling up the onboard coresight memory buffer. 30 At typical coresight system would look like this:: 85 a way to aggregate and distribute signals between CoreSight components. 87 The coresight framework provides a central point to represent, configure and 88 manage coresight devices on a platform. This first implementation centers on 133 See Documentation/devicetree/bindings/arm/coresight.txt for details. [all …]
D	coresight-trbe.rst	`15 gets plugged in as a coresight sink device because the corresponding trace 18 The TRBE is not compliant to CoreSight architecture specifications, but is 19 driven via the CoreSight driver framework to support the ETE (which is 20 CoreSight compliant) integration. 25 The TRBE devices appear on the existing coresight bus alongside the other 26 coresight devices:: 28 >$ ls /sys/bus/coresight/devices 33 >$ ls /sys/bus/coresight/devices/trbe0/`
D	coresight-cpu-debug.rst	2 Coresight CPU Debug Module 11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual 107 power down in the way that the CoreSight / Debug designers anticipated. 120 See Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt for details. 183 coresight-cpu-debug 850000.debug: CPU[0]: 184 coresight-cpu-debug 850000.debug: EDPRSR: 00000001 (Power:On DLK:Unlock) 185 coresight-cpu-debug 850000.debug: EDPCSR: handle_IPI+0x174/0x1d8 186 coresight-cpu-debug 850000.debug: EDCIDSR: 00000000 187 …coresight-cpu-debug 850000.debug: EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMI… 188 coresight-cpu-debug 852000.debug: CPU[1]: [all …]
D	coresight-ect.rst	4 CoreSight Embedded Cross Trigger (CTI & CTM). 13 The CoreSight Cross Trigger Interface (CTI) is a hardware device that takes 41 CoreSight devices on the trace data path. When these devices are enabled the 50 The hardware trigger signals can also be connected to non-CoreSight devices 62 The CTI devices appear on the existing CoreSight bus alongside the other 63 CoreSight devices:: 65 >$ ls /sys/bus/coresight/devices 71 can be associated with other CoreSight devices, or other system hardware 74 >$ ls /sys/bus/coresight/devices/etm0/cti_cpu0 91 * ``mgmt``: the standard CoreSight management registers. [all …]
D	coresight-config.rst	4 CoreSight System Configuration Manager 13 The CoreSight System Configuration manager is an API that allows the 14 programming of the CoreSight system with pre-defined configurations that 17 Many CoreSight components can be programmed in complex ways - especially ETMs. 18 In addition, components can interact across the CoreSight system, often via 26 This section introduces the basic concepts of a CoreSight system configuration. 32 A feature is a named set of programming for a CoreSight device. The programming 38 CoreSight device is registered with the configuration manager. 66 Users can update parameter values using the configfs API for the CoreSight 113 associated feature 'strobing' that works on ETMv4 CoreSight Devices. [all …]
/Linux-v5.15/arch/arm/boot/dts/
D	hip04.dtsi	272 compatible = "arm,coresight-etb10", "arm,primecell"; 287 compatible = "arm,coresight-etb10", "arm,primecell"; 302 compatible = "arm,coresight-etb10", "arm,primecell"; 317 compatible = "arm,coresight-etb10", "arm,primecell"; 332 compatible = "arm,coresight-tpiu", "arm,primecell"; 350 compatible = "arm,coresight-static-replicator"; 385 compatible = "arm,coresight-static-replicator"; 420 compatible = "arm,coresight-static-replicator"; 454 compatible = "arm,coresight-static-replicator"; 485 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; [all …]
/Linux-v5.15/drivers/acpi/
D	acpi_amba.c	`24 {"ARMHC500", 0}, /* ARM CoreSight ETM4x / 25 {"ARMHC501", 0}, / ARM CoreSight ETR / 26 {"ARMHC502", 0}, / ARM CoreSight STM / 27 {"ARMHC503", 0}, / ARM CoreSight Debug / 28 {"ARMHC979", 0}, / ARM CoreSight TPIU / 29 {"ARMHC97C", 0}, / ARM CoreSight SoC-400 TMC, SoC-600 ETF/ETB / 30 {"ARMHC98D", 0}, / ARM CoreSight Dynamic Replicator / 31 {"ARMHC9CA", 0}, / ARM CoreSight CATU / 32 {"ARMHC9FF", 0}, / ARM CoreSight Dynamic Funnel */`
/Linux-v5.15/arch/arm64/boot/dts/sprd/
D	sc9863a.dtsi	188 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 212 compatible = "arm,coresight-tmc", "arm,primecell"; 228 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 277 compatible = "arm,coresight-tmc", "arm,primecell"; 302 compatible = "arm,coresight-tmc", "arm,primecell"; 327 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 364 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 413 compatible = "arm,coresight-etm4x", "arm,primecell"; 430 compatible = "arm,coresight-etm4x", "arm,primecell"; 447 compatible = "arm,coresight-etm4x", "arm,primecell"; [all …]

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