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Searched +full:coresight +full:- +full:tmc (Results 1 – 25 of 29) sorted by relevance

12

/Linux-v6.1/Documentation/ABI/testing/
Dsysfs-bus-coresight-devices-tmc1 What: /sys/bus/coresight/devices/<memory_map>.tmc/trigger_cntr
10 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rsz
14 Description: (Read) Defines the size, in 32-bit words, of the local RAM buffer.
17 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/sts
21 Description: (Read) Shows the value held by the TMC status register. The value
24 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rrp
28 Description: (Read) Shows the value held by the TMC RAM Read Pointer register
33 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rwp
37 Description: (Read) Shows the value held by the TMC RAM Write Pointer register
39 the CoreSight bus into the Trace RAM. The value is read directly
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/Linux-v6.1/drivers/hwtracing/coresight/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for CoreSight drivers.
5 obj-$(CONFIG_CORESIGHT) += coresight.o
6 coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
7 coresight-sysfs.o coresight-syscfg.o coresight-config.o \
8 coresight-cfg-preload.o coresight-cfg-afdo.o \
9 coresight-syscfg-configfs.o
10 obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
11 coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
12 coresight-tmc-etr.o
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Dcoresight-tmc-core.c1 // SPDX-License-Identifier: GPL-2.0
4 * Description: CoreSight Trace Memory Controller driver
20 #include <linux/dma-mapping.h>
24 #include <linux/coresight.h>
27 #include "coresight-priv.h"
28 #include "coresight-tmc.h"
36 struct coresight_device *csdev = drvdata->csdev; in tmc_wait_for_tmcready()
37 struct csdev_access *csa = &csdev->access; in tmc_wait_for_tmcready()
41 dev_err(&csdev->dev, in tmc_wait_for_tmcready()
42 "timeout while waiting for TMC to be Ready\n"); in tmc_wait_for_tmcready()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Coresight configuration
5 menuconfig CORESIGHT config
6 tristate "CoreSight Tracing Support"
13 This framework provides a kernel interface for the CoreSight debug
15 a topological view of the CoreSight components based on a DT
20 module will be called coresight.
22 if CORESIGHT
24 tristate "CoreSight Link and Sink drivers"
26 This enables support for CoreSight link and sink drivers that are
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Dcoresight-tmc-etf.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/coresight.h>
12 #include "coresight-priv.h"
13 #include "coresight-tmc.h"
14 #include "coresight-etm-perf.h"
21 CS_UNLOCK(drvdata->base); in __tmc_etb_enable_hw()
26 writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE); in __tmc_etb_enable_hw()
30 drvdata->base + TMC_FFCR); in __tmc_etb_enable_hw()
32 writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG); in __tmc_etb_enable_hw()
35 CS_LOCK(drvdata->base); in __tmc_etb_enable_hw()
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Dcoresight-tmc.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/dma-mapping.h>
45 /* TMC_CTL - 0x020 */
47 /* TMC_STS - 0x00C */
53 * TMC_AXICTL - 0x110
55 * TMC AXICTL format for SoC-400
56 * Bits [0-1] : ProtCtrlBit0-1
57 * Bits [2-5] : CacheCtrlBits 0-3 (AXCACHE)
60 * Bits [8-11] : WrBurstLen
61 * Bits [12-31] : Reserved.
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Dcoresight-tmc-etr.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/coresight.h>
9 #include <linux/dma-mapping.h>
17 #include "coresight-catu.h"
18 #include "coresight-etm-perf.h"
19 #include "coresight-priv.h"
20 #include "coresight-tmc.h"
30 * etr_perf_buffer - Perf buffer used for ETR
31 * @drvdata - The ETR drvdaga this buffer has been allocated for.
32 * @etr_buf - Actual buffer used by the ETR
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Dcoresight-catu.c1 // SPDX-License-Identifier: GPL-2.0
5 * Coresight Address Translation Unit support
12 #include <linux/dma-mapping.h>
17 #include "coresight-catu.h"
18 #include "coresight-priv.h"
19 #include "coresight-tmc.h"
22 dev_get_drvdata(csdev->dev.parent)
43 * ------------------------------------
44 * | Address [63-12] | SBZ | V|
45 * ------------------------------------
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/Linux-v6.1/Documentation/devicetree/bindings/arm/
Darm,coresight-tmc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm CoreSight Trace Memory Controller
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
16 CoreSight components are compliant with the ARM CoreSight architecture
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Darm,embedded-trace-extension.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 ---
5 $id: "http://devicetree.org/schemas/arm/arm,embedded-trace-extension.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Suzuki K Poulose <suzuki.poulose@arm.com>
12 - Mathieu Poirier <mathieu.poirier@linaro.org>
16 allows tracing the CPU execution. It overlaps with the CoreSight ETMv4
18 The trace generated by the ETE could be stored via legacy CoreSight
19 components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer
21 legacy CoreSight components, a node must be listed per instance, along
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Darm,coresight-catu.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm Coresight Address Translation Unit (CATU)
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
16 CoreSight components are compliant with the ARM CoreSight architecture
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/Linux-v6.1/arch/arm64/boot/dts/hisilicon/
Dhi3660-coresight.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 * dtsi for Hisilicon Hi3660 Coresight
6 * Copyright (C) 2016-2018 HiSilicon Ltd.
15 compatible = "arm,coresight-etm4x", "arm,primecell";
18 clock-names = "apb_pclk";
21 out-ports {
24 remote-endpoint =
32 compatible = "arm,coresight-etm4x", "arm,primecell";
35 clock-names = "apb_pclk";
38 out-ports {
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Dhi6220-coresight.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * dtsi file for Hisilicon Hi6220 coresight
14 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
17 clock-names = "apb_pclk";
19 out-ports {
22 remote-endpoint =
28 in-ports {
31 remote-endpoint =
39 compatible = "arm,coresight-tmc", "arm,primecell";
42 clock-names = "apb_pclk";
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/Linux-v6.1/arch/arm64/boot/dts/sprd/
Dsc9863a.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/clock/sprd,sc9863a-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #address-cells = <2>;
15 #size-cells = <0>;
17 cpu-map {
48 compatible = "arm,cortex-a55";
50 enable-method = "psci";
51 cpu-idle-states = <&CORE_PD>;
56 compatible = "arm,cortex-a55";
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Dsc9860.dtsi6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
16 #address-cells = <2>;
17 #size-cells = <0>;
19 cpu-map {
53 compatible = "arm,cortex-a53";
55 enable-method = "psci";
56 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
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Dsc9836.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #address-cells = <2>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a53";
23 enable-method = "psci";
28 compatible = "arm,cortex-a53";
30 enable-method = "psci";
35 compatible = "arm,cortex-a53";
37 enable-method = "psci";
42 compatible = "arm,cortex-a53";
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/Linux-v6.1/Documentation/trace/coresight/
Dcoresight.rst2 Coresight - HW Assisted Tracing on ARM
9 ------------
11 Coresight is an umbrella of technologies allowing for the debugging of ARM
24 flows through the coresight system (via ATB bus) using links that are connecting
25 the emanating source to a sink(s). Sinks serve as endpoints to the coresight
28 host without fear of filling up the onboard coresight memory buffer.
30 At typical coresight system would look like this::
38 0 CPU 0<-->: C : 0 CPU 0<-->: C : : C : @ STM @ || System ||
39 |->0000000 : T : |->0000000 : T : : T :<--->@@@@@ || Memory ||
40 | #######<-->: I : | #######<-->: I : : I : @@@<-| ||||||||||||
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/Linux-v6.1/drivers/acpi/
Dacpi_amba.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/clk-provider.h>
24 {"ARMH0330", 0}, /* ARM DMA Controller DMA-330 */
25 {"ARMHC500", 0}, /* ARM CoreSight ETM4x */
26 {"ARMHC501", 0}, /* ARM CoreSight ETR */
27 {"ARMHC502", 0}, /* ARM CoreSight STM */
28 {"ARMHC503", 0}, /* ARM CoreSight Debug */
29 {"ARMHC979", 0}, /* ARM CoreSight TPIU */
30 {"ARMHC97C", 0}, /* ARM CoreSight SoC-400 TMC, SoC-600 ETF/ETB */
31 {"ARMHC98D", 0}, /* ARM CoreSight Dynamic Replicator */
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/Linux-v6.1/arch/arm64/boot/dts/arm/
Djuno-cs-r1r2.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
8 clock-names = "apb_pclk";
9 power-domains = <&scpi_devpd 0>;
10 out-ports {
13 remote-endpoint = <&etf1_in_port>;
17 in-ports {
27 compatible = "arm,coresight-tmc", "arm,primecell";
31 clock-names = "apb_pclk";
32 power-domains = <&scpi_devpd 0>;
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Djuno-base.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 clock-frequency = <50000000>;
14 #address-cells = <1>;
15 #size-cells = <1>;
19 frame-number = <1>;
31 #mbox-cells = <1>;
33 clock-names = "apb_pclk";
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/Linux-v6.1/arch/arm64/boot/dts/qcom/
Dmsm8916.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8916.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
13 #include <dt-bindings/thermal/thermal.h>
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Dmsm8998.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/power/qcom-rpmpd.h>
10 #include <dt-bindings/gpio/gpio.h>
13 interrupt-parent = <&intc>;
15 qcom,msm-id = <292 0x0>;
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Dsm8150.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/power/qcom-rpmpd.h>
10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
13 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
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/Linux-v6.1/arch/arm/boot/dts/
Dimx7s.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
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Dqcom-msm8974.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
10 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
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