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/Linux-v6.1/Documentation/devicetree/bindings/arm/
Darm,coresight-static-replicator.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-static-replicator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm CoreSight Static Trace Bus Replicator
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
16 CoreSight components are compliant with the ARM CoreSight architecture
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/Linux-v6.1/drivers/hwtracing/coresight/
Dcoresight-replicator.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
5 * Description: CoreSight Replicator driver
20 #include <linux/coresight.h>
22 #include "coresight-priv.h"
27 DEFINE_CORESIGHT_DEVLIST(replicator_devs, "replicator");
30 * struct replicator_drvdata - specifics associated to a replicator component
33 * @atclk: optional clock for the core parts of the replicator.
46 static void dynamic_replicator_reset(struct replicator_drvdata *drvdata) in dynamic_replicator_reset()
48 struct coresight_device *csdev = drvdata->csdev; in dynamic_replicator_reset()
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Dcoresight-platform.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/coresight.h>
21 #include "coresight-priv.h"
26 static int coresight_alloc_conns(struct device *dev, in coresight_alloc_conns()
29 if (pdata->nr_outport) { in coresight_alloc_conns()
30 pdata->conns = devm_kcalloc(dev, pdata->nr_outport, in coresight_alloc_conns()
31 sizeof(*pdata->conns), GFP_KERNEL); in coresight_alloc_conns()
32 if (!pdata->conns) in coresight_alloc_conns()
33 return -ENOMEM; in coresight_alloc_conns()
39 static struct device *
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/Linux-v6.1/arch/arm/boot/dts/
Dhip04.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-2014 HiSilicon Ltd.
6 * Copyright (C) 2013-2014 Linaro Ltd.
12 /* memory bus is 64-bit */
13 #address-cells = <2>;
14 #size-cells = <2>;
21 compatible = "hisilicon,hip04-bootwrapper";
22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
26 #address-cells = <1>;
27 #size-cells = <0>;
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Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
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Dvexpress-v2p-ca15_a7.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
8 * HBI-0249A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15_CA7";
18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
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Dimx7s.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
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Dste-dbx5x0.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/reset/stericsson,db8500-prcc-reset.h>
9 #include <dt-bindings/mfd/dbx500-prcmu.h>
10 #include <dt-bindings/arm/ux500_pm_domains.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
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Dqcom-apq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
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/Linux-v6.1/Documentation/trace/coresight/
Dcoresight.rst2 Coresight - HW Assisted Tracing on ARM
9 ------------
11 Coresight is an umbrella of technologies allowing for the debugging of ARM
24 flows through the coresight system (via ATB bus) using links that are connecting
25 the emanating source to a sink(s). Sinks serve as endpoints to the coresight
28 host without fear of filling up the onboard coresight memory buffer.
30 At typical coresight system would look like this::
38 0 CPU 0<-->: C : 0 CPU 0<-->: C : : C : @ STM @ || System ||
39 |->0000000 : T : |->0000000 : T : : T :<--->@@@@@ || Memory ||
40 | #######<-->: I : | #######<-->: I : : I : @@@<-| ||||||||||||
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/Linux-v6.1/arch/arm64/boot/dts/hisilicon/
Dhi3660-coresight.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 * dtsi for Hisilicon Hi3660 Coresight
6 * Copyright (C) 2016-2018 HiSilicon Ltd.
15 compatible = "arm,coresight-etm4x", "arm,primecell";
18 clock-names = "apb_pclk";
21 out-ports {
24 remote-endpoint =
32 compatible = "arm,coresight-etm4x", "arm,primecell";
35 clock-names = "apb_pclk";
38 out-ports {
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Dhi6220-coresight.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * dtsi file for Hisilicon Hi6220 coresight
14 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
17 clock-names = "apb_pclk";
19 out-ports {
22 remote-endpoint =
28 in-ports {
31 remote-endpoint =
39 compatible = "arm,coresight-tmc", "arm,primecell";
42 clock-names = "apb_pclk";
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/Linux-v6.1/drivers/acpi/
Dacpi_amba.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/clk-provider.h>
22 static const struct acpi_device_id amba_id_list[] = {
24 {"ARMH0330", 0}, /* ARM DMA Controller DMA-330 */
25 {"ARMHC500", 0}, /* ARM CoreSight ETM4x */
26 {"ARMHC501", 0}, /* ARM CoreSight ETR */
27 {"ARMHC502", 0}, /* ARM CoreSight STM */
28 {"ARMHC503", 0}, /* ARM CoreSight Debug */
29 {"ARMHC979", 0}, /* ARM CoreSight TPIU */
30 {"ARMHC97C", 0}, /* ARM CoreSight SoC-400 TMC, SoC-600 ETF/ETB */
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