Searched full:core0 (Results 1 – 25 of 159) sorted by relevance
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/Linux-v6.6/drivers/remoteproc/ |
D | ti_k3_r5_remoteproc.c | 430 * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to 433 * private to each core. Only Core0 needs to be unhalted for running the 500 * both cores, but with only Core0 unhalted. This function re-uses the same 529 * mode requires the boot vector to be configured only for Core0, and then 531 * first followed by Core0. The Split-mode requires that Core0 to be maintained 533 * always only after Core0 is started). 535 * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to execute 536 * code, so only Core0 needs to be unhalted. The function uses the same logic 595 * performed first on Core0 followed by Core1. The Split-mode requires that 596 * Core0 to be maintained always in a higher power state that Core1 (implying [all …]
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/Linux-v6.6/arch/powerpc/boot/dts/fsl/ |
D | p1020rdb-pc_camp_core0.dts | 3 * P1020 RDB-PC Core0 Device Tree Source in CAMP mode. 7 * This dts file allows core0 to have memory, l2, i2c, spi, gpio, tdm, dma, usb, 10 * Please note to add "-b 0" for core0's dts compiling.
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D | mpc8572ds_camp_core0.dts | 3 * MPC8572 DS Core0 Device Tree Source in CAMP mode. 7 * This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0,
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/Linux-v6.6/Documentation/devicetree/bindings/gpu/ |
D | brcm,bcm-v3d.yaml | 26 - description: core0 register (required) 34 - const: core0 70 reg-names = "hub", "core0", "bridge", "gca";
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D | arm,mali-bifrost.yaml | 183 - const: core0 206 - const: core0 224 - const: core0 240 - const: core0
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/Linux-v6.6/Documentation/devicetree/bindings/media/ |
D | qcom,sdm845-venus.yaml | 38 video-core0: 93 - video-core0 116 video-core0 {
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D | qcom,sdm845-venus-v2.yaml | 55 video-core0: 83 - video-core0 115 video-core0 {
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/Linux-v6.6/arch/arm/boot/dts/intel/axm/ |
D | axm5516-cpus.dtsi | 15 core0 { 29 core0 { 43 core0 { 57 core0 {
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/Linux-v6.6/arch/arm64/boot/dts/amd/ |
D | amd-seattle-cpus.dtsi | 10 core0 { 18 core0 { 26 core0 { 34 core0 {
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/Linux-v6.6/Documentation/devicetree/bindings/cpu/ |
D | cpu-topology.txt | 194 core0 { 214 core0 { 236 core0 { 255 core0 { 413 core0 { 428 core0 { 507 core0 {
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/Linux-v6.6/arch/arm64/boot/dts/hisilicon/ |
D | hip05.dtsi | 27 core0 { 41 core0 { 55 core0 { 69 core0 {
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D | hip07.dtsi | 27 core0 { 42 core0 { 57 core0 { 72 core0 { 87 core0 { 102 core0 { 117 core0 { 132 core0 { 147 core0 { 162 core0 { [all …]
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/Linux-v6.6/arch/arm64/boot/dts/amlogic/ |
D | meson-g12b.dtsi | 18 core0 { 28 core0 {
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D | amlogic-t7.dtsi | 19 core0 { 34 core0 {
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D | meson-gxm.dtsi | 15 core0 { 30 core0 {
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/Linux-v6.6/arch/arm64/boot/dts/ti/ |
D | k3-am654.dtsi | 16 core0 { 26 core0 {
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D | k3-j784s4.dtsi | 29 core0 { 47 core0 { 274 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
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/Linux-v6.6/sound/soc/intel/skylake/ |
D | bxt-sst.c | 113 dev_err(ctx->dev, "dsp core0/1 power up failed\n"); in sst_bxt_prepare_fw() 121 /* Step 3: Unset core0 reset state & unstall/run core0 */ in sst_bxt_prepare_fw() 299 "D0i3 allowed when only core0 running:Exit\n"); in bxt_set_dsp_D0i3() 451 dev_err(ctx->dev, "Failed to set core0 to D0 state\n"); in bxt_set_dsp_D0()
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D | skl-sst-dsp.c | 281 dev_err(ctx->dev, "dsp core0 reset fail: %d\n", ret); in skl_dsp_boot() 287 dev_err(ctx->dev, "dsp core0 start fail: %d\n", ret); in skl_dsp_boot() 293 dev_err(ctx->dev, "dsp core0 disable fail: %d\n", ret); in skl_dsp_boot()
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/Linux-v6.6/arch/arm64/boot/dts/apple/ |
D | t6002.dtsi | 28 core0 { 37 core0 { 52 core0 {
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D | t600x-common.dtsi | 20 core0 { 29 core0 { 44 core0 {
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/Linux-v6.6/arch/arm/boot/dts/samsung/ |
D | exynos5422-cpus.dtsi | 26 core0 { 41 core0 {
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D | exynos5420-cpus.dtsi | 27 core0 { 42 core0 {
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/Linux-v6.6/arch/arm64/boot/dts/freescale/ |
D | imx8qm.dtsi | 27 vpu-core0 = &vpu_core0; 38 core0 { 53 core0 {
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/Linux-v6.6/Documentation/devicetree/bindings/remoteproc/ |
D | ti,k3-r5f-rproc.yaml | 21 called "Single-CPU" mode, where only Core0 is used, but with ability to use 144 # The following properties are mandatory for R5F Core0 in both LockStep and Split 296 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
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