| /Linux-v6.1/drivers/media/platform/qcom/venus/ |
| D | hfi_parser.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include "core.h"
17 static void init_codecs(struct venus_core *core) in init_codecs() argument
19 struct hfi_plat_caps *caps = core->caps, *cap; in init_codecs()
22 for_each_set_bit(bit, &core->dec_codecs, MAX_CODEC_NUM) { in init_codecs()
23 cap = &caps[core->codecs_count++]; in init_codecs()
24 cap->codec = BIT(bit); in init_codecs()
25 cap->domain = VIDC_SESSION_TYPE_DEC; in init_codecs()
26 cap->valid = false; in init_codecs()
29 for_each_set_bit(bit, &core->enc_codecs, MAX_CODEC_NUM) { in init_codecs()
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| /Linux-v6.1/arch/arm/mach-omap2/ |
| D | powerdomains44xx_data.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2009-2011 Texas Instruments, Inc.
6 * Copyright (C) 2009-2011 Nokia Corporation
9 * Benoit Cousson (b-cousson@ti.com)
14 * with the public linux-omap@vger.kernel.org mailing list and the
16 * up-to-date with the file contents.
24 #include "prcm-common.h"
26 #include "prm-regbits-44xx.h"
30 /* core_44xx_pwrdm: CORE power domain */
33 .voltdm = { .name = "core" },
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| D | powerdomains54xx_data.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Benoit Cousson (b-cousson@ti.com)
13 * with the public linux-omap@vger.kernel.org mailing list and the
15 * up-to-date with the file contents.
23 #include "prcm-common.h"
28 /* core_54xx_pwrdm: CORE power domain */
31 .voltdm = { .name = "core" },
54 /* abe_54xx_pwrdm: Audio back end power domain */
57 .voltdm = { .name = "core" },
74 /* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
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| /Linux-v6.1/Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,apr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
20 - qcom,apr-v2
21 - qcom,gpr
23 power-domains:
26 qcom,apr-domain:
30 Selects the processor domain for apr
32 2 = PC Domain
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| /Linux-v6.1/Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra20-pmc.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
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| /Linux-v6.1/Documentation/networking/ |
| D | regulatory.rst | 1 .. SPDX-License-Identifier: GPL-2.0
15 ---------------------------------------
19 to the kernel one regulatory domain to be used as the central
20 core regulatory domain all wireless devices should adhere to.
23 -------------------------------------------
25 When the regulatory domain is first set up, the kernel will request a
31 ---------------------------------------------------------------
33 Userspace gets a regulatory domain in the kernel by having
38 is CRDA - central regulatory domain agent. Its documented here:
43 it needs a new regulatory domain. A udev rule can be put in place
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| /Linux-v6.1/arch/arm64/boot/dts/apple/ |
| D | t8103-pmgr.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 ps_sbr: power-controller@100 {
11 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
13 #power-domain-cells = <0>;
14 #reset-cells = <0>;
16 apple,always-on; /* Core device */
19 ps_aic: power-controller@108 {
20 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
22 #power-domain-cells = <0>;
23 #reset-cells = <0>;
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| /Linux-v6.1/arch/powerpc/perf/ |
| D | hv-24x7-domains.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * DOMAIN(name, num, index_kind, is_physical)
9 * @num: The number corresponding to the domain as given in
10 * documentation. We assume the catalog domain and the hcall
11 * domain have the same numbering (so far they do), but this
15 * within the given domain. Must fit the parsing rules of the
18 * @is_physical: True if the domain is physical, false otherwise (if virtual).
21 * physical core and virtual processor in 24x7 Counters specifications.
24 DOMAIN(PHYS_CHIP, 0x01, chip, true)
25 DOMAIN(PHYS_CORE, 0x02, core, true)
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| /Linux-v6.1/Documentation/devicetree/bindings/clock/ |
| D | renesas,rzg2l-cpg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
18 - The CPG block generates various core clocks,
19 - The Module Standby Mode block provides two functions:
20 1. Module Standby, providing a Clock Domain to control the clock supply
27 - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five
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| D | renesas,cpg-mssr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
18 - The CPG block generates various core clocks,
19 - The MSSR block provides two functions:
20 1. Module Standby, providing a Clock Domain to control the clock supply
27 - renesas,r7s9210-cpg-mssr # RZ/A2
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| D | qcom,sc7180-lpasscorecc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm LPASS Core Clock Controller Binding for SC7180
10 - Taniya Das <tdas@codeaurora.org>
13 Qualcomm LPASS core clock control module which supports the clocks and
17 - dt-bindings/clock/qcom,lpasscorecc-sc7180.h
22 - qcom,sc7180-lpasshm
23 - qcom,sc7180-lpasscorecc
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| D | qcom,sc7280-lpasscorecc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscorecc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm LPASS Core & Audio Clock Controller Binding for SC7280
10 - Taniya Das <tdas@codeaurora.org>
13 Qualcomm LPASS core and audio clock control module which supports the
17 - dt-bindings/clock/qcom,lpasscorecc-sc7280.h
18 - dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
23 clock-names: true
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| /Linux-v6.1/include/net/ |
| D | regulatory.h | 7 * Copyright 2008-2009 Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
28 * enum environment_cap - Environment parsed from country IE
41 * struct regulatory_request - used to keep track of regulatory requests
46 * can be used by the wireless core to deal with conflicts
52 * regulatory domain. We have a few special codes:
53 * 00 - World regulatory domain
54 * 99 - built by driver but a specific alpha2 cannot be determined
55 * 98 - result of an intersection between two regulatory domains
56 * 97 - regulatory domain has not yet been configured
57 * @dfs_region: If CRDA responded with a regulatory domain that requires
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| /Linux-v6.1/Documentation/devicetree/bindings/soc/imx/ |
| D | fsl,imx8mm-disp-blk-ctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MM DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
15 peripherals located in the DISP domain of the SoC.
20 - const: fsl,imx8mm-disp-blk-ctrl
21 - const: syscon
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| D | fsl,imx8mp-media-blk-ctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Elder <paul.elder@ideasonboard.com>
13 The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
15 peripherals within the MEDIAMIX domain.
20 - const: fsl,imx8mp-media-blk-ctrl
21 - const: syscon
26 '#power-domain-cells':
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| /Linux-v6.1/Documentation/devicetree/bindings/regulator/ |
| D | nvidia,tegra-regulators-coupling.txt | 4 NVIDIA Tegra SoC's have a mandatory voltage-coupling between regulators.
9 ------------------------
11 On Tegra20 SoC's there are 3 coupled regulators: CORE, RTC and CPU.
12 The CORE and RTC voltages shall be in a range of 170mV from each other
16 ------------------------
18 On Tegra30 SoC's there are 2 coupled regulators: CORE and CPU. The CORE
19 and CPU voltages shall be in a range of 300mV from each other and CORE
24 - nvidia,tegra-core-regulator: Boolean property that designates regulator
25 as the "Core domain" voltage regulator.
26 - nvidia,tegra-rtc-regulator: Boolean property that designates regulator
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| D | fixed-regulator.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/fixed-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Girdwood <lgirdwood@gmail.com>
11 - Mark Brown <broonie@kernel.org>
14 Any property defined as part of the core regulator binding, defined in
16 expected to have the regulator-min-microvolt and regulator-max-microvolt
20 - $ref: "regulator.yaml#"
21 - if:
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| /Linux-v6.1/Documentation/devicetree/bindings/remoteproc/ |
| D | qcom,adsp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 firmware on the Qualcomm ADSP Hexagon core.
19 - qcom,msm8226-adsp-pil
20 - qcom,msm8974-adsp-pil
21 - qcom,msm8996-adsp-pil
22 - qcom,msm8996-slpi-pil
23 - qcom,msm8998-adsp-pas
[all …]
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| D | qcom,q6v5.txt | 4 on the Qualcomm Hexagon core.
6 - compatible:
10 "qcom,q6v5-pil",
11 "qcom,ipq8074-wcss-pil"
12 "qcom,qcs404-wcss-pil"
13 "qcom,msm8916-mss-pil",
14 "qcom,msm8974-mss-pil"
15 "qcom,msm8996-mss-pil"
16 "qcom,msm8998-mss-pil"
17 "qcom,sdm845-mss-pil"
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| /Linux-v6.1/kernel/irq/ |
| D | ipi.c | 1 // SPDX-License-Identifier: GPL-2.0
15 * irq_reserve_ipi() - Setup an IPI to destination cpumask
16 * @domain: IPI domain
23 int irq_reserve_ipi(struct irq_domain *domain, in irq_reserve_ipi() argument
30 if (!domain ||!irq_domain_is_ipi(domain)) { in irq_reserve_ipi()
31 pr_warn("Reservation on a non IPI domain\n"); in irq_reserve_ipi()
32 return -EINVAL; in irq_reserve_ipi()
37 return -EINVAL; in irq_reserve_ipi()
43 return -EINVAL; in irq_reserve_ipi()
46 if (irq_domain_is_ipi_single(domain)) { in irq_reserve_ipi()
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| /Linux-v6.1/arch/powerpc/platforms/powernv/ |
| D | opal-imc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include <asm/imc-pmu.h>
57 struct imc_mem_info *ptr = pmu_ptr->mem_info; in export_imc_mode_and_cmd()
64 while (ptr->vbase != NULL) { in export_imc_mode_and_cmd()
65 loc = (u64)(ptr->vbase) + cb_offset; in export_imc_mode_and_cmd()
67 sprintf(mode, "imc_mode_%d", (u32)(ptr->id)); in export_imc_mode_and_cmd()
72 sprintf(cmd, "imc_cmd_%d", (u32)(ptr->id)); in export_imc_mode_and_cmd()
91 nr_chips = of_property_count_u32_elems(node, "chip-id"); in imc_get_mem_addr_nest()
93 return -ENODEV; in imc_get_mem_addr_nest()
97 return -ENOMEM; in imc_get_mem_addr_nest()
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| /Linux-v6.1/Documentation/devicetree/bindings/display/msm/ |
| D | gmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
2 # Copyright 2019-2020, The Linux Foundation, All Rights Reserved
4 ---
7 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
12 - Rob Clark <robdclark@gmail.com>
16 to members of the Adreno A6xx GPU family. The GMU provides on-device power
23 - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
24 - const: qcom,adreno-gmu
30 reg-names:
38 clock-names:
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-qcom-hw.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
21 - description: v1 of CPUFREQ HW
23 - const: qcom,cpufreq-hw
25 - description: v2 of CPUFREQ HW (EPSS)
27 - enum:
28 - qcom,sm6375-cpufreq-epss
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| /Linux-v6.1/Documentation/devicetree/bindings/bus/ |
| D | qcom,ssc-block-bus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Srba <Michael.Srba@seznam.cz>
20 The SSC (Snapdragon Sensor Core) block contains a gpio controller, i2c/spi/uart
21 controllers, a hexagon core, and a clock controller which provides clocks for
27 - const: qcom,msm8998-ssc-block-bus
28 - const: qcom,ssc-block-bus
32 - description: SSCAON_CONFIG0 registers
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| /Linux-v6.1/Documentation/sound/soc/ |
| D | dapm.rst | 11 such, can easily co-exist with the other PM systems.
14 all power switching is done within the ASoC core. No code changes or
25 Codec bias domain
26 VREF, VMID (core codec and audio power)
31 Platform/Machine domain
38 Path domain
44 Stream domain
60 Audio DAPM widgets fall into a number of types:-
127 (Widgets are defined in include/sound/soc-dapm.h)
130 There are convenience macros defined in soc-dapm.h that can be used to quickly
[all …]
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