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/Linux-v5.4/Documentation/devicetree/bindings/clock/
Drenesas,cpg-mstp-clocks.txt1 * Renesas CPG Module Stop (MSTP) Clocks
3 The CPG can gate SoC device clocks. The gates are organized in groups of up to
6 This device tree binding describes a single 32 gate clocks group per node.
7 Clocks are referenced by user nodes by the MSTP node phandle and the clock
13 - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
14 - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks
15 - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
16 - "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks
17 - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
18 - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
[all …]
Dexynos5433-clock.txt10 which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
11 domains and bus clocks.
13 which generates clocks for LLI (Low Latency Interface) IP.
15 which generates clocks for DRAM Memory Controller domain.
17 which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
19 which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
21 which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
23 which generates clocks for G2D/MDMA IPs.
25 which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
27 which generates clocks for Cortex-A5/BUS/AUDIO clocks.
[all …]
Dexynos5260-clock.txt5 generate and supply clocks to various hardware blocks within
10 available clocks are defined as preprocessor macros in
14 External clocks:
16 There are several clocks that are generated outside the SoC. It
26 Phy clocks:
28 There are several clocks which are generated by specific PHYs.
29 These clocks are fed into the clock controller and then routed to
30 the hardware blocks. These clocks are defined as fixed clocks in the
71 - clocks: list of clock identifiers which are fed as the input to
73 the input clocks for a given controller.
[all …]
Dexynos7-clock.txt5 generate and supply clocks to various hardware blocks within
10 available clocks are defined as preprocessor macros in
14 External clocks:
16 There are several clocks that are generated outside the SoC. It
45 - clocks: list of clock identifiers which are fed as the input to
47 find the input clocks for a given controller.
49 - clock-names: list of names of clocks which are fed as the input
52 Input clocks for top0 clock controller:
60 Input clocks for top1 clock controller:
67 Input clocks for ccore clock controller:
[all …]
/Linux-v5.4/drivers/clk/mediatek/
DKconfig20 This driver supports MediaTek MT2701 basic clocks.
26 This driver supports MediaTek MT2701 mmsys clocks.
32 This driver supports MediaTek MT2701 imgsys clocks.
38 This driver supports MediaTek MT2701 vdecsys clocks.
44 This driver supports MediaTek MT2701 hifsys clocks.
50 This driver supports MediaTek MT2701 ethsys clocks.
56 This driver supports MediaTek MT2701 bdpsys clocks.
62 This driver supports Mediatek MT2701 audsys clocks.
68 This driver supports MediaTek MT2701 g3dsys clocks.
76 This driver supports MediaTek MT2712 basic clocks.
[all …]
/Linux-v5.4/arch/arm/boot/dts/
Ds3c2416.dtsi30 clocks: clock-controller@4c000000 { label
41 clocks = <&clocks PCLK_PWM>;
49 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
50 <&clocks SCLK_UART>;
57 clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
58 <&clocks SCLK_UART>;
65 clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
66 <&clocks SCLK_UART>;
75 clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
76 <&clocks SCLK_UART>;
[all …]
Ds5pv210.dtsi61 external-clocks {
90 clocks = <&clocks CLK_NANDXL>, <&clocks DOUT_FLASH>;
102 clocks: clock-controller@e0100000 { label
106 clocks = <&xxti>, <&xusbxti>;
142 clocks = <&clocks CLK_PDMA0>;
154 clocks = <&clocks CLK_PDMA1>;
169 clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>;
185 clocks = <&clocks SCLK_SPI1>, <&clocks CLK_SPI1>;
199 clocks = <&clocks CLK_KEYIF>;
209 clocks = <&clocks CLK_I2C0>;
[all …]
Domap3xxx-clocks.dtsi17 …clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck…
24 clocks = <&osc_sys_ck>;
34 clocks = <&osc_sys_ck>;
42 clocks = <&dpll3_ck>;
50 clocks = <&dpll3_m2_ck>;
58 clocks = <&dpll4_ck>;
66 clocks = <&dpll3_m2x2_ck>;
74 clocks = <&sys_ck>;
84 clocks = <&core_96m_fck>, <&mcbsp_clks>;
92 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
[all …]
Domap24xx-clocks.dtsi11 clocks = <&func_96m_ck>, <&mcbsp_clks>;
19 clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
25 clocks = <&func_96m_ck>, <&mcbsp_clks>;
33 clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
77 clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>;
85 clocks = <&aplls_clkin_ck>;
93 clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>;
102 clocks = <&osc_ck>;
124 clocks = <&sys_ck>, <&sys_ck>;
131 clocks = <&sys_ck>;
[all …]
Ds3c64xx.dtsi68 clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
69 <&clocks SCLK_MMC0>;
79 clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
80 <&clocks SCLK_MMC1>;
90 clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>,
91 <&clocks SCLK_MMC2>;
101 clocks = <&clocks PCLK_WDT>;
110 clocks = <&clocks PCLK_IIC0>;
123 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
124 <&clocks SCLK_UART>;
[all …]
Domap54xx-clocks.dtsi17 clocks = <&pad_clks_src_ck>;
37 clocks = <&slimbus_src_clk>;
105 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
112 clocks = <&dpll_abe_ck>;
118 clocks = <&dpll_abe_x2_ck>;
127 clocks = <&dpll_abe_m2x2_ck>;
135 clocks = <&dpll_abe_m2x2_ck>;
144 clocks = <&aess_fclk>;
153 clocks = <&dpll_abe_m2x2_ck>;
161 clocks = <&dpll_abe_x2_ck>;
[all …]
Domap2430-clocks.dtsi12 clocks = <&func_96m_ck>, <&mcbsp_clks>;
19 clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
25 clocks = <&func_96m_ck>, <&mcbsp_clks>;
33 clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
39 clocks = <&func_96m_ck>, <&mcbsp_clks>;
47 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
55 clocks = <&dsp_fck>;
63 clocks = <&dsp_fck>;
73 clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
79 clocks = <&core_ck>;
[all …]
Ddra7xx-clocks.dtsi11 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
17 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
23 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
29 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
107 clocks = <&sys_clkin1>;
199 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
206 clocks = <&dpll_abe_ck>;
212 clocks = <&dpll_abe_x2_ck>;
223 clocks = <&dpll_abe_m2x2_ck>;
232 clocks = <&dpll_abe_ck>;
[all …]
Dste-nomadik-stn8815.dtsi40 clocks = <&timclk>, <&pclk>;
49 clocks = <&timclk>, <&pclk>;
64 clocks = <&pclk>;
78 clocks = <&pclk>;
92 clocks = <&pclk>;
107 clocks = <&pclk>;
215 clocks = <&mxtal>;
223 clocks = <&mxtal>;
230 clocks = <&pll1>;
238 clocks = <&hclk>;
[all …]
Dam43xx-clocks.dtsi11 clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
19 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
27 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
35 clocks = <&sys_clkin_ck>;
43 clocks = <&sys_clkin_ck>;
51 clocks = <&sys_clkin_ck>;
59 clocks = <&sys_clkin_ck>;
67 clocks = <&sys_clkin_ck>;
75 clocks = <&sys_clkin_ck>;
83 clocks = <&sys_clkin_ck>;
[all …]
Dsocfpga.dtsi85 clocks = <&l4_main_clk>;
104 clocks = <&can0_clk>;
113 clocks = <&can1_clk>;
122 clocks {
151 clocks = <&osc1>;
157 clocks = <&main_pll>;
165 clocks = <&main_pll>;
173 clocks = <&main_pll>, <&osc1>;
181 clocks = <&main_pll>;
188 clocks = <&main_pll>;
[all …]
Domap34xx-omap36xx-clocks.dtsi11 clocks = <&l4_ick>;
19 clocks = <&security_l4_ick2>;
27 clocks = <&security_l4_ick2>;
35 clocks = <&security_l4_ick2>;
43 clocks = <&security_l4_ick2>;
51 clocks = <&dpll4_m5x2_ck>;
60 clocks = <&l4_ick>;
68 clocks = <&core_96m_fck>;
76 clocks = <&l3_ick>;
84 clocks = <&security_l3_ick>;
[all …]
Dam33xx-clocks.dtsi11 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
19 clocks = <&sys_clkin_ck>;
27 clocks = <&sys_clkin_ck>;
35 clocks = <&sys_clkin_ck>;
43 clocks = <&sys_clkin_ck>;
51 clocks = <&sys_clkin_ck>;
59 clocks = <&sys_clkin_ck>;
67 clocks = <&sys_clkin_ck>;
75 clocks = <&sys_clkin_ck>;
83 clocks = <&sys_clkin_ck>;
[all …]
Domap44xx-clocks.dtsi23 clocks = <&pad_clks_src_ck>;
49 clocks = <&slimbus_src_clk>;
135 clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
142 clocks = <&dpll_abe_ck>;
149 clocks = <&dpll_abe_x2_ck>;
160 clocks = <&dpll_abe_m2x2_ck>;
168 clocks = <&dpll_abe_m2x2_ck>;
178 clocks = <&dpll_abe_x2_ck>;
189 clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
197 clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
[all …]
Dr7s72100.dtsi30 /* Fixed factor clocks */
34 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
48 clocks = <&cpg_clocks R7S72100_CLK_I>;
53 /* External clocks */
64 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
72 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
121 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
134 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
147 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
160 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
[all …]
/Linux-v5.4/arch/arm64/boot/dts/xilinx/
Dzynqmp-clk.dtsi76 clocks = <&clk100 &clk100>;
80 clocks = <&clk100 &clk100>;
84 clocks = <&clk600>, <&clk100>;
88 clocks = <&clk600>, <&clk100>;
92 clocks = <&clk600>, <&clk100>;
96 clocks = <&clk600>, <&clk100>;
100 clocks = <&clk600>, <&clk100>;
104 clocks = <&clk600>, <&clk100>;
108 clocks = <&clk600>, <&clk100>;
112 clocks = <&clk600>, <&clk100>;
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/display/
Dst,stih4xx.txt15 - clocks: from common clock binding: handle hardware IP needed clocks, the
16 number of clocks may depend of the SoC type.
17 See ../clocks/clock-bindings.txt for details.
18 - clock-names: names of the clocks listed in clocks property in the same
33 - clocks: from common clock binding: handle hardware IP needed clocks, the
34 number of clocks may depend of the SoC type.
35 See ../clocks/clock-bindings.txt for details.
36 - clock-names: names of the clocks listed in clocks property in the same
66 - clocks: from common clock binding: handle hardware IP needed clocks, the
67 number of clocks may depend of the SoC type.
[all …]
/Linux-v5.4/drivers/clk/bcm/
Dclk-bcm281xx.c27 .clocks = CLOCKS("ref_crystal"),
43 .clocks = CLOCKS("bbl_32k",
52 .clocks = CLOCKS("ref_crystal",
61 .clocks = CLOCKS("var_312m",
85 .clocks = CLOCKS("ref_crystal",
104 .clocks = CLOCKS("ref_crystal",
116 .clocks = CLOCKS("ref_crystal",
128 .clocks = CLOCKS("ref_crystal",
140 .clocks = CLOCKS("ref_crystal",
152 .clocks = CLOCKS("ref_crystal",
[all …]
Dclk-bcm21664.c25 .clocks = CLOCKS("ref_crystal"),
43 .clocks = CLOCKS("bbl_32k",
67 .clocks = CLOCKS("ref_crystal",
79 .clocks = CLOCKS("ref_crystal",
91 .clocks = CLOCKS("ref_crystal",
103 .clocks = CLOCKS("ref_crystal",
114 .clocks = CLOCKS("ref_32k"), /* Verify */
119 .clocks = CLOCKS("ref_32k"), /* Verify */
124 .clocks = CLOCKS("ref_32k"), /* Verify */
129 .clocks = CLOCKS("ref_32k"), /* Verify */
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/clock/ti/davinci/
Dda8xx-cfgchip.txt1 Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP clocks
5 gates. This document describes the bindings for those clocks.
10 USB PHY clocks
13 - compatible: shall be "ti,da830-usb-phy-clocks".
15 - clocks: phandles to the parent clocks corresponding to clock-names
18 This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz
26 - clocks: phandle to the parent clock
34 - clocks: phandle to the parent clock
42 - clocks: phandles to the parent clocks corresponding to clock-names
50 - clocks: phandles to the parent clocks corresponding to clock-names
[all …]

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