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/Linux-v6.1/arch/arm/boot/dts/
Dmeson6.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
13 #address-cells = <1>;
14 #size-cells = <0>;
18 compatible = "arm,cortex-a9";
19 next-level-cache = <&L2>;
25 compatible = "arm,cortex-a9";
26 next-level-cache = <&L2>;
32 compatible = "simple-bus";
34 #address-cells = <1>;
35 #size-cells = <1>;
[all …]
Dmeson8.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8-gpio.h>
9 #include <dt-bindings/power/meson8-power.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
20 #address-cells = <1>;
21 #size-cells = <0>;
[all …]
Dmeson8b.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/power/meson8-power.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
13 #include <dt-bindings/thermal/thermal.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
[all …]
Dmstar-v7.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/mstar-msc313-mpll.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/clock/
Darmada3700-xtal-clock.txt1 * Xtal Clock bindings for Marvell Armada 37xx SoCs
3 Marvell Armada 37xx SoCs allow to determine the xtal clock frequencies by
8 See Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
11 - compatible : shall be one of the following:
12 "marvell,armada-3700-xtal-clock"
13 - #clock-cells : from common clock binding; shall be set to 0
16 - clock-output-names : from common clock binding; allows overwrite default clock
17 output names ("xtal")
20 pinctrl_nb: pinctrl-nb@13800 {
21 compatible = "armada3710-nb-pinctrl", "syscon", "simple-mfd";
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Dsilabs,si5351.txt1 Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
5 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
7 The Si5351a/b/c are programmable i2c clock generators with up to 8 output
8 clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
9 3 output clocks are accessible. The internal structure of the clock
15 - compatible: shall be one of the following:
16 "silabs,si5351a" - Si5351a, QFN20 package
17 "silabs,si5351a-msop" - Si5351a, MSOP10 package
18 "silabs,si5351b" - Si5351b, QFN20 package
19 "silabs,si5351c" - Si5351c, QFN20 package
[all …]
Damlogic,gxbb-clkc.txt1 * Amlogic GXBB Clock and Reset Unit
3 The Amlogic GXBB clock controller generates and supplies clock to various
8 - compatible: should be:
9 "amlogic,gxbb-clkc" for GXBB SoC,
10 "amlogic,gxl-clkc" for GXL and GXM SoC,
11 "amlogic,axg-clkc" for AXG SoC.
12 "amlogic,g12a-clkc" for G12A SoC.
13 "amlogic,g12b-clkc" for G12B SoC.
14 "amlogic,sm1-clkc" for SM1 SoC.
15 - clocks : list of clock phandle, one for each entry clock-names.
[all …]
Dmarvell,armada-3700-uart-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/marvell,armada-3700-uart-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 - Pali Rohár <pali@kernel.org>
13 const: marvell,armada-3700-uart-clock
17 - description: UART Clock Control Register
18 - description: UART 2 Baud Rate Divisor Register
23 "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal"
24 UART clock can use one from this set and when more are provided
[all …]
Damlogic,gxbb-aoclkc.txt1 * Amlogic GXBB AO Clock and Reset Unit
3 The Amlogic GXBB AO clock controller generates and supplies clock to various
4 controllers within the Always-On part of the SoC.
8 - compatible: value should be different for each SoC family as :
9 - GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
10 - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
11 - GXM (S912) : "amlogic,meson-gxm-aoclkc"
12 - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
13 - G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc"
14 followed by the common "amlogic,meson-gx-aoclkc"
[all …]
Dnxp,lpc3220-clk.txt1 NXP LPC32xx Clock Controller
4 - compatible: should be "nxp,lpc3220-clk"
5 - reg: should contain clock controller registers location and length
6 - #clock-cells: must be 1, the cell holds id of a clock provided by the
7 clock controller
8 - clocks: phandles of external oscillators, the list must contain one
10 - clock-names: list of external oscillator clock names, must contain
11 "xtal_32k" and may have optional "xtal"
17 compatible = "simple-bus";
19 #address-cells = <1>;
[all …]
Damlogic,meson8-ddr-clkc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic DDR Clock Controller
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
15 - amlogic,meson8-ddr-clkc
16 - amlogic,meson8b-ddr-clkc
24 clock-names:
26 - const: xtal
[all …]
Dlpc1850-cgu.txt1 * NXP LPC1850 Clock Generation Unit (CGU)
4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
15 - Above text taken from NXP LPC1850 User Manual.
18 This binding uses the common clock binding:
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
[all …]
Dpistachio-clock.txt1 Imagination Technologies Pistachio SoC clock controllers
4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
6 from the device-tree.
9 ----------------
11 There are three external inputs to the clock controllers which should be
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
17 Core clock controller:
[all …]
Dsilabs,si5341.txt2 i2c clock generator.
6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
12 The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
15 The internal structure of the clock generators can be found in [2].
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
33 - compatible: shall be one of the following:
34 "silabs,si5340" - Si5340 A/B/C/D
35 "silabs,si5341" - Si5341 A/B/C/D
[all …]
/Linux-v6.1/arch/arm64/boot/dts/amlogic/
Dmeson-gxbb.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "meson-gx.dtsi"
7 #include "meson-gx-mali450.dtsi"
8 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
9 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
10 #include <dt-bindings/clock/gxbb-clkc.h>
11 #include <dt-bindings/clock/gxbb-aoclkc.h>
12 #include <dt-bindings/reset/gxbb-aoclkc.h>
15 compatible = "amlogic,meson-gxbb";
19 compatible = "amlogic,meson-gxbb-usb2-phy";
[all …]
Dmeson-a1.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/gpio/meson-a1-gpio.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <2>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a35";
[all …]
Dmeson-gxl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-gx.dtsi"
8 #include <dt-bindings/clock/gxbb-clkc.h>
9 #include <dt-bindings/clock/gxbb-aoclkc.h>
10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
14 compatible = "amlogic,meson-gxl";
18 compatible = "amlogic,meson-gxl-usb-ctrl";
21 #address-cells = <2>;
22 #size-cells = <2>;
[all …]
Dmeson-s4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/gpio/gpio.h>
12 #address-cells = <2>;
13 #size-cells = <0>;
17 compatible = "arm,cortex-a35";
19 enable-method = "psci";
24 compatible = "arm,cortex-a35";
26 enable-method = "psci";
[all …]
Dmeson-g12-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/phy/phy.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/clock/g12a-clkc.h>
9 #include <dt-bindings/clock/g12a-aoclkc.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/serial/
Damlogic,meson-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/serial/amlogic,meson-uart.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Neil Armstrong <neil.armstrong@linaro.org>
15 of SoCs, and can be present either in the "Always-On" power domain or the
16 "Everything-Else" power domain.
18 The particularity of the "Always-On" Serial Interface is that the hardware
19 is active since power-on and does not need any clock gating and is usable
25 - description: Always-on power domain UART controller
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/timer/
Damlogic,meson6-timer.txt5 - compatible : should be "amlogic,meson6-timer"
6 - reg : Specifies base physical address and size of the registers.
7 - interrupts : The four interrupts, one for each timer event
8 - clocks : phandles to the pclk (system clock) and XTAL clocks
9 - clock-names : must contain "pclk" and "xtal"
14 compatible = "amlogic,meson6-timer";
20 clocks = <&xtal>, <&clk81>;
21 clock-names = "xtal", "pclk";
/Linux-v6.1/drivers/clk/mvebu/
Darmada-37xx-xtal.c1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell Armada 37xx SoC xtal clocks
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 #include <linux/clk-provider.h>
21 struct device_node *np = pdev->dev.of_node; in armada_3700_xtal_clock_probe()
22 const char *xtal_name = "xtal"; in armada_3700_xtal_clock_probe()
30 xtal_hw = devm_kzalloc(&pdev->dev, sizeof(*xtal_hw), GFP_KERNEL); in armada_3700_xtal_clock_probe()
32 return -ENOMEM; in armada_3700_xtal_clock_probe()
36 parent = np->parent; in armada_3700_xtal_clock_probe()
38 dev_err(&pdev->dev, "no parent\n"); in armada_3700_xtal_clock_probe()
[all …]
/Linux-v6.1/include/linux/platform_data/
Dsi5351.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Si5351A/B/C programmable clock generator platform_data.
10 * enum si5351_pll_src - Si5351 pll clock source
12 * @SI5351_PLL_SRC_XTAL: pll source clock is XTAL input
13 * @SI5351_PLL_SRC_CLKIN: pll source clock is CLKIN input (Si5351C only)
22 * enum si5351_multisynth_src - Si5351 multisynth clock source
24 * @SI5351_MULTISYNTH_SRC_VCO0: multisynth source clock is VCO0
25 * @SI5351_MULTISYNTH_SRC_VCO1: multisynth source clock is VCO1/VXCO
34 * enum si5351_clkout_src - Si5351 clock output clock source
36 * @SI5351_CLKOUT_SRC_MSYNTH_N: clkout N source clock is multisynth N
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/media/
Damlogic,meson-ir-tx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/media/amlogic,meson-ir-tx.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Viktor Prutyanov <viktor.prutyanov@phystech.edu>
21 - const: amlogic,meson-ir-tx
22 - items:
23 - const: amlogic,meson-g12a-ir-tx
24 - const: amlogic,meson-ir-tx
35 clock-names:
[all …]
/Linux-v6.1/drivers/clk/renesas/
Drcar-usb2-clock-sel.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas R-Car USB2.0 clock selector
7 * Based on renesas-cpg-mssr.c
13 #include <linux/clk-provider.h>
32 { .id = "hs-usb-if", },
41 bool xtal; member
47 u16 val = readw(priv->base + USB20_CLKSET0); in usb2_clock_sel_enable_extal_only()
50 priv->extal, priv->xtal, val); in usb2_clock_sel_enable_extal_only()
52 if (priv->extal && !priv->xtal && val != CLKSET0_EXTAL_ONLY) in usb2_clock_sel_enable_extal_only()
53 writew(CLKSET0_EXTAL_ONLY, priv->base + USB20_CLKSET0); in usb2_clock_sel_enable_extal_only()
[all …]

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